Conditional disable symbols should not systematically alter validity of FPGA bitfiles ...

[manu.NET]

Hello,

I have a LabView project which includes a Windows part and a FPGA part.

To simulate my windows part i use Conditional Disable Symbols in order to bypass the FPGA calls. ( Ex: DEBUG = TRUE/FALSE)

These project Conditional Disable Symbols are not used im my FPGA Vi's. 

BUT, when i change the Conditional Disable Symbols values ... i have to rebuild my FPGA code !  This is not good !

The "Bitfile validity" check should be a little more intelligent.

The "bitfile update detection" should only take in account the Conditional Disable Symbols it uses.

Thank for reading.

Manu.

[gsussman]

Are you certain that your Windows code and FPGA code don't contain some of the same VIs?

If you are not using LV2010 and seperating your block diagrams and actual compiled code then the Windows code and FPGA code will continually fight back and forth as to which target's executable code is contained in the VI.

I have had similar things happen with Windows/RT systems.

[manu.NET]

Hi gsussman,

I currently use LV2010.

My FPGA code use some Windows VI's, but not those with conditional disable structures.

But i don't think this is the problem, because i replace all my conditional disable structures with simple case structures ...

and yet i can change/compile my windows part without affecting the FPGA code.

I think the problem is only linked to an "FPGA change detection mecanism" which takes in account the condititional disable symbols.

In other words, i think that a global, quick CRC calculation is done, to know if a FPGA compilation is required or not.

And this CRC calculation certainly takes in account the values of the conditionnal disable symbols.

Manu.net