 Intaris
		
			Intaris
		
		
		 on 
    
	
		
		
		12-13-2012
	
		
		07:51 AM
	
	
	
	
	
	
	
	
	
	
	
	
	
	
		
	
				
		
			2 Comments (2 New)
		
		
		
		
		
	
			 on 
    
	
		
		
		12-13-2012
	
		
		07:51 AM
	
	
	
	
	
	
	
	
	
	
	
	
	
	
		
	
				
		
			2 Comments (2 New)
		
	
		Having recently attempted to get started with Simulation for debugging my FPGA code I found out that apparently the built-in LV support for native LV testbenches using simulated FPGA is supported only for ModelSim SE.
This is a shame since ISim is included with the FPGA toolkit.
If feasible, expanding the functionality to allos co-simulation with ISim would be a rather splendid idea ideed!
Shane.
You must be a registered user to add a comment. If you've already registered, sign in. Otherwise, register and sign in.