Can support for simulating CLIP nodes (as can be done with IP Integration Node) be provided in LabVIEW FPGA?
I think this is the default. I dropped an IP integration node on my block diagram and I was able to run it in simulation. I believe during the setup of the node, the xilinx synthesizer generates a DLL in the background.
Indeed IP Integration Node does simulate.
CLIP does not. The containing VI will 'run' in simulation mode but the outputs are not expected to be meaningful.
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