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Intaris

Explicit Constant Folding

Status: New

As LabVIEW evolves more and more, the compiler takes over an awful lot of code optimisation for us.  This leads us to situations where relatively large and important pieces of code can be evaluated at compile time and constant folded which can greatly aid execution speed.  This is good.

 

Constant folding can be a great aid when programming but at the moment, it's usage is a bit "hit and miss" due to the opaqueness of the process.  We already have constant folding highlighting, which really helps things (even if the feedback is sometimes very hard to understand).  But this doesn't always give us enough feedback.

 

What I would like is the option to declare a portion of code as "Requires constant folding" (like a "Precompile" structure).  In this way, I can, as a programmer, designate some code which is meant to be evaluated at compile time.  If the compiler is unable to constant fold this code, then the VI should be broken.  My motivations are three-fold.

  1. Sometimes we want to specifically make use of the constant folding capabilities of the compiler, but a small change can result in the code no longer being constant folded.  I would like explicit feedback when code I want constant folded is not constant foldable.
  2. I have no idea whether code complexity has an effect on the ability to constant fold.  Other compiler optimisations (Like unbundle-unbundle inplaceness) are dependent on code complexity.  Explicit declaration is not code complexity dependent.
  3. When looking at FPGA designs, the ability to perform constant folding of data otherwise requiring resources or affecting performance is very powerful.  In such a "Constant folding" code, we could also allow mathematical functions to be used which are otherwise not supported on the target (max/min of an array in a timed loop for example), or creating default data for an array (to be used as Block RAM) based on an existing equation where constants are defined as DBL.

 

One example of FPGA code is automatic latency balancing of several parameter pathways into a process where the code accepts abstract parameter objects whose latency is queried via a dynamic dispatch VI which simply returns a constant.  I use dependency injection to tell the sub-VIs which communication pathways they are being given and they can then query the latency and do some static timing calculations for the delays required on different pathways.  Tests have shown that this is constant folded and that it is thus possible to write very robust FPGA code which auto-adjusts request indices for parameters in multiplexed code.  At the moment, things seem to work but the ability to specifically designate such code as being constant folded would be welcome to make sure I don't accidentally produce a version which doesn't actually return a constant (and my compiles fail, I get timing errors, or just over-use resources)....  In the code below, all of the code circled in blue is constant-folded when compiling the FPGA code.  In the sub-VIs I have to do some awkward calculations because certain functioanlity is not available on FPGA.  By defining this code as requiring explicit constant folding, I could theoretically utilise the full palette of LV functions and also be guaranteed a compile error (LabVIEW error, not Xilinx) if the code thus designated can not be constant folded.

 

2016-09-15 10_13_00.png

 

So in a way, it's similar to the In place element structure which, when all goes well, should not be needed but there are cases (I've run into some myself) where either small changes in code can make the desired operation impossible or where the code complexity can cause the optimisation to not be performed.  As such, it is still required at times to explicitly designate some code paths as being In-Place.  I would like to have the same functionality for "Constant folding".

23 Comments
Intaris
Proven Zealot

Me too.

Hooovahh
Proven Zealot

Well I'm a fan (and kudo'd) but some of the conserns are valid.  Having the target perform the compilation and effecivly paste the result on the BD as a constant will likely cover every use I've had for this, but I understand its issues.

 

What if on the structure itself you had a way of right clicking and saying compile this structure, and on it you had the option to compile using the target, or the host, and then that result would be saved in that structure.  If it hadn't been explicity selected where the result comes from it would default to the host.  I realize it maybe a bit odd to compile a structure for an FPGA since that requires a seperate compiler and connection, and all sorts of things, but I assume technically it could be done.

David-A
NI Employee (retired)

If you want to detect the absence of a consant value on the FPGA there are already VIs that we ship that you can use to do this. The Basic Elements library is an Instrument Design Library that ships with some of our drivers (e.g. FlexRIO 15.1 and later). In that Basic Elements library is a public vi called Assert Constant.vi that can be used to to throw an error at intermediary file generation if does not detect a consant value wired to its input. 

 

<LabVIEW>\instr.lib\_niInstr\Basic Elements\v1\FPGA\Public\Assert Constant.vi

 

We use it to ensure that a user has not incidently connected a control or something upstream of the node that would prevent certain optimizations from occuring. An example of where we have used the Assert Constant.vi is in the Constant Operation.vi.

 

<LabVIEW>\instr.lib\_niInstr\Data Formatting\v1\FPGA\Public\Constant Operation.vi

 

 

 

Intaris
Proven Zealot

David, that's a great peice of information...  I'll look into that immediately.  Sounds like it's a great way to have complete peace of mind regarding the extent of the constant folding being performed.

Intaris
Proven Zealot

OK, looking at how this is implemented raises way more questions than answers.....  Very interesting (and unlocked).....  Can this be reliably be leveraged?

David-A
NI Employee (retired)

The driver groups that leverage the libraries in the <LabVIEW>\instr.lib\_niInstr directory also maintain them. The intention is that any publicly scoped vi that is a member of one of those libraries is intended to be used by end users. Most of the drivers that install them to disk will add them to the functions palette to encourage their use.

Intaris
Proven Zealot

David,

 

i just got around to actually putting this VI into my code to check for constant folding but it's telling me that my code isn't constant folded......  I'm not sure that's true.

 

At which stage of the compile process does this error get raised? I have a bunch of LVOOP objects passing their "latency" values (DD Method, constants wired to output terminals) which should - according to my understanding of LVOOP on FPGA - get constant folded......

 

Will this VI catch these cases?  Do I need to label the wire specifically and do a search of the Xilinx Log to see if it is constant folded there?  Is there something preventing my code being constant folded?

 

I ask here isntead of opening up a regular forum post because my original idea was of this nature... The check should be at the latest possible stage int he compilation process, just before things are handed over to Xilinx.

David-A
NI Employee (retired)

I've used the assert constant in a few classes when doing fpga development. Seems to work fine. The read numeric method shown below does what you mentioned, connects a numeric constant to terminal. This compiles. So a static dispatch should correctly propagate constants.

constantfold_statoic_dispatch.PNG

I would take a second look at what you've got upstream of the node in question to make sure its as constant as you think it is. If you think you've found a bug in the way LabVIEW propagates constants you may want to post an example so we can file a corrective action request.

Intaris
Proven Zealot

Ah, but I don't have Static dispatch, I have Dynamic Dispatch....... It becomes Static during the FPGA compile process, but perhaps this check is prior?

David-A
NI Employee (retired)

I could have phrased that better. The code snippet shown above is using dynamic dispatch. And as you mentioned any DD used on an fpga diagram must resolve to static dispatch at compile time.

 

In either case, the assert constant performs its check after the compiler has resolved the class.