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Intaris

Explicit Constant Folding

Status: New

As LabVIEW evolves more and more, the compiler takes over an awful lot of code optimisation for us.  This leads us to situations where relatively large and important pieces of code can be evaluated at compile time and constant folded which can greatly aid execution speed.  This is good.

 

Constant folding can be a great aid when programming but at the moment, it's usage is a bit "hit and miss" due to the opaqueness of the process.  We already have constant folding highlighting, which really helps things (even if the feedback is sometimes very hard to understand).  But this doesn't always give us enough feedback.

 

What I would like is the option to declare a portion of code as "Requires constant folding" (like a "Precompile" structure).  In this way, I can, as a programmer, designate some code which is meant to be evaluated at compile time.  If the compiler is unable to constant fold this code, then the VI should be broken.  My motivations are three-fold.

  1. Sometimes we want to specifically make use of the constant folding capabilities of the compiler, but a small change can result in the code no longer being constant folded.  I would like explicit feedback when code I want constant folded is not constant foldable.
  2. I have no idea whether code complexity has an effect on the ability to constant fold.  Other compiler optimisations (Like unbundle-unbundle inplaceness) are dependent on code complexity.  Explicit declaration is not code complexity dependent.
  3. When looking at FPGA designs, the ability to perform constant folding of data otherwise requiring resources or affecting performance is very powerful.  In such a "Constant folding" code, we could also allow mathematical functions to be used which are otherwise not supported on the target (max/min of an array in a timed loop for example), or creating default data for an array (to be used as Block RAM) based on an existing equation where constants are defined as DBL.

 

One example of FPGA code is automatic latency balancing of several parameter pathways into a process where the code accepts abstract parameter objects whose latency is queried via a dynamic dispatch VI which simply returns a constant.  I use dependency injection to tell the sub-VIs which communication pathways they are being given and they can then query the latency and do some static timing calculations for the delays required on different pathways.  Tests have shown that this is constant folded and that it is thus possible to write very robust FPGA code which auto-adjusts request indices for parameters in multiplexed code.  At the moment, things seem to work but the ability to specifically designate such code as being constant folded would be welcome to make sure I don't accidentally produce a version which doesn't actually return a constant (and my compiles fail, I get timing errors, or just over-use resources)....  In the code below, all of the code circled in blue is constant-folded when compiling the FPGA code.  In the sub-VIs I have to do some awkward calculations because certain functioanlity is not available on FPGA.  By defining this code as requiring explicit constant folding, I could theoretically utilise the full palette of LV functions and also be guaranteed a compile error (LabVIEW error, not Xilinx) if the code thus designated can not be constant folded.

 

2016-09-15 10_13_00.png

 

So in a way, it's similar to the In place element structure which, when all goes well, should not be needed but there are cases (I've run into some myself) where either small changes in code can make the desired operation impossible or where the code complexity can cause the optimisation to not be performed.  As such, it is still required at times to explicitly designate some code paths as being In-Place.  I would like to have the same functionality for "Constant folding".

23 Comments
AristosQueue (NI)
NI Employee (retired)

Wow, David-A, I had never heard of that VI on the FPGA side of the world. In combination with malleable VIs, that could be quite powerful. I've been looking into ways of extending malleable VIs, and a lot of those depend upon users being able to specify parameters that are known at compile time but propagate into the subroutine on wires. If FPGA already has things that need to be compile-time known, you might already be able to use the malleable VIs to create some useful code.

Intaris
Proven Zealot

In combination with this VI, I have some interesting remarks:

 

  1. In my code, the function I am using to calculate dependent delays and perform autobalancing of parallel code pathways IS producing constant-folded code.
  2. It stops doing this if I start with an object, add data fields and then call the function within a Static VI within a dynamic Dispatch VI.  Exactly which step leads to the loss of constant folding I do not know yet.  The only inputs to the algorithm are via a "Get Latency" DD function, ALL of which simply have a constant wired to an indicator on the FP.  I'm trying to get a test case I can submit.
  3. Most importantly: The VI which is doing the constant check is essentially already executing code on the Host when attempting a compile of the FPGA VI.  Check out the corresponding file int he "ModGen" folder where the "constant folding" VI is found.  Here we have some very non-FPGA code doing their thing at the start of each compilation process.  THIS I would like to be able to abuse for creating initialisation values for my FPGA code.  As we here see, the code is NOT being run on the FPGA, is not limited in its DBL or SGL support and can use the full slew of LV functions available.........
Intaris
Proven Zealot

Quick update:

I found the issue with the usage of the Assert Constant VI.....

 

In my code I have create a cluster of delays which need to be constant-folded otherwise they produce some incredibly inefficient code..... (I'm pretty sure they ARE constant folded because my code compiles 🙂 ).

 

According to the NI Examples, I should perform an "Equals" comparison on any single wire to check if it is a constant. 

 

 

If I do this on each cluster entry individually and AND the values, it works fine.2017-10-24 14_23_00-AO Handler 3xSC5.vi Block Diagram on NewFPGA merge.lvproj_FPGA Target _.png

 

 

 

If I do a cluster compare and choose "Compare aggregates" it works fine.2017-10-24 14_23_23-AO Handler 3xSC5.vi Block Diagram on NewFPGA merge.lvproj_FPGA Target _.png

 

 

If I do a cluster compare with "Compare elements" and then do a "Cluster to Array" followed by "AND Array" it tells me that the code is not constant folded.....

2017-10-24 14_28_06-AO Handler 3xSC5.vi Block Diagram on NewFPGA merge.lvproj_FPGA Target _.png

 

 

This is more of a bug report than anything else really.... unless there's a good reason why this should be so.