LabVIEW FPGA. Allow coercion dots to cause an error

[Al1234]

Can we cause an error if there are coercion dots on the block diagrams for FPGA targets?

This would be helpful for finding wrongly connected fixed size arrays especially at the interface of a subVI - the coercion dots are easy to miss but usually mean something is seriously wrong!

This could be a setting in the "Tools | Options | Block Diagram" dialog.

[MattN]

Do you see this as a feature that should be strictly limited to FPGA Targets, or would you also find it useful for general LabVIEW programming?  FPGA uses preallocated/sized types (fixed sized arrays and fixed point) more than most other targets, but even in LabVIEW for Windows a coercion dot may mean you're losing data. 

While not as tightly coupled as an edit-time error, I believe the VI Analyzer has a test that will identify coercion dots in a VI. 

[Al1234]

Personally I like to try and remove all coercion dots on any targets but admit defeat with dividing integers, operations on some enums etc. where to remove the dot makes for clumsy, unnecessary code!

I've coded LabVIEW for 14 years and only just noticed the "show warnings" tick box on the error list dialog! - perfect. Make the coercion dots appear as warnings...

[Darren]

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