Normalize terminals height for timed structures and FPGA nodes

[raphschru]

Starting from LV 2023 Q1, the terminals height of some nodes was harmonized to 16 pixels to improve diagram readability by reducing the amount of needed wire bends.

Some candidates for this harmonization were omitted though:

 - Data nodes of timed structures (timed loop, timed sequence).

 - I think pretty much all of FPGA nodes (IO nodes / methods / properties, FIFO / memory / register / handshake methods, IP integration, high-troughput math nodes, ...).

Example with a Timed Loop:

The idea is to also allow RT and FPGA developments to benefit from this harmonization.

[crossrulz]

Related idea that was completed with 2023Q1: Same Height of Unbundle by Name / Terminal / Local Variable 

With that said, I am all for standardizing terminal sizes.