ADC with very low DNL for pulse height histogram MCA ?

[Steve Parus]

I'm looking for an 100 kHz or faster analog to digital converter with
very low DNL ( much lower than 0.1 lsb or 10%) to be used for pulse
height MCA analysis by creating a histogram of digitized count
values. Standard PCI interface cards have DNL of 0.2 lsb which
produces noisy histograms when repeatedly digitizing a triangle wave
spanning the entire adc input range. PCI card would be best, but
external device or just the adc chip itself would be useable.
Wilkinson style is one known for such low DNL.

[LocalDSP]

To help converging toward your actual requirements, could you be a little more specific on what exactly you need?

Remember that the actual DNL accuracy specified in "% of lsb" depends on the actual resolution (lsb) of your converter, so 40% for an 18 bit converter is as accurate as 10% for a 16 bit converter. In other words, "percent of full-scale" would be a more useful specification.

Also, Sigma-Delta converters tend to have significantly better DNL specifications than "traditional" sample rate type converters, but they may not track ramps or triangular wave as well. Would that be a problem for you?

Do you need a true integrating ADC?

Have you looked at the NI-5911?
http://www.ni.com/pdf/products/us/4mi444-447.pdf
This PCI board is a multi-bit SD-AD
C that will give you more than 19 bit INL at 100 kHz rate and much better DNL. ... but it's a sigma-delta type.

[Steve Parus]

Application is time correlated single photon counting to measure
nanosecond fluorescent lifetimes. A laser pulse generates a start
pulse. The first photon emitted from the sample generates a stop
pulse. The time difference is converted to a voltage pulse (0 to
+10V), 2 usec duration (I could extend that with an external
sample/hold) by a time-to-amplitude converter. The overall lifetime
of the sample is constructed by repeating this at least tens of
thousands of times. For each laser shot, the voltage pulse is
digitized and its binary code summed into a histogram bin. A plot is
made of number of occurances vs adc binary code value. At least 12
bits of resolution is desired. The pulses to be digitized occur
randomly in time at least 10 usec apart (maybe 100 usec).

For accurate data, the width of each histogram bin should be equal. I
test this by making a histogram from a triangle wave. The number of
occurances vs raw adc counts should be flat. Instead, it exhibits
variations of 20% (equivalent to 0.2 lsb of dnl).

So what I'd like is an adc with bin widths equal to say 1% that can
digitize a voltage within 10 usec. Its type should not really matter
as long as it can accomplish this.

A 20% deviation in adc bin width seems like a high value for something
electronic in nature ike this. What is it that makes this not
typically so, since most adc's has 0.2 lsb DNL specs ?


On Mon, 5 Apr 2004 21:43:39 -0500 (CDT), LocalDSP wrote:

>To help converging toward your actual requirements, could you be a
>little more specific on what exactly you need?
>
>Remember that the actual DNL accuracy specified in "% of lsb" depends
>on the actual resolution (lsb) of your converter, so 40% for an 18 bit
>converter is as accurate as 10% for a 16 bit converter. In other
>words, "percent of full-scale" would be a more useful specification.
>
>Also, Sigma-Delta converters tend to have significantly better DNL
>specifications than "traditional" sample rate type converters, but
>they may not track ramps or triangular wave as well. Would that be a
>problem for you?
>
>Do you need a true integrating ADC?
>
>Have you looked at the NI-5911?
>http://www.ni.com/pdf/products/us/4mi444-447.pdf
>This PCI board is a multi-bit SD-ADC that will give you more than 19
>bit INL at 100 kHz rate and much better DNL. ... but it's a
>sigma-delta type.

[LocalDSP]

For that type of pulsing application a sigma-delta ADC will not work, you need a "sampling rate" type converter.

If you say that 12 bit would be sufficient, again if you then use a good 16 bit ADC with, say, 0.5 lsb DNL, you can accumulate your data into a "12 bit" histogram (4096 bins) and achieve a 0.5/16 = 0.03125 lsb DNL (in a 12 bit world). Even accumulating in a 14 bit histogram your DNL would still be better than 0.5/4 = 0.125 lsb.

You mention that you are testing your DNL using a triangular waveform. Are you sure the non-linearities you are measuring are not created by the generator? Are you accumulating your histogram long enough to randomize the number of events falling in each bin?

What ADC or PCI board are you using today and h
ow do you generate your triangular test signal?