Add delay between each byte sent with NI I2C IP on LabVIEW FPGA

[mtuell]

Hello,

I'm working on a project using a cRIO-9048 and an NI-9402 module to speak I2C to an external chip. After a bunch of work discovering that the 9402 is the only module that will work and downgrading to LabVIEW 2019 SP1 32-bit, which seems to be the only version that works, I finally have a working I2C bus using the NI I2C IP package. 

I'm seeing some confusing behaviors including some NAKs from the external chip. The datasheet recommends including 100us delays after each byte sent on the I2C bus, so I'd like to try that to see if it fixes my problem. As far as I can see on my scope and logic analyzer, there are currently no delays between bytes.

I'm using the "master" part of the example code as the FPGA side of my application. Looking into the subVIs it's not obvious how to add the delay. There's a lot I don't understand about LabVIEW though, so I thought someone here might be able to help. Any information is appreciated.

I've attached my test FPGA VI for reference.

Thanks,

Mitcham

[mtuell]

Update:

After some studying how the code works, I was able to add an additional piece to I2C Master.vi. It delays the passing of a "valid" signal from the byte controller back to the I2C Master state machine by a set number of clock cycles. I have it set to 4000, which is 100us at 40MHz clock. It seems to work, but there might be edge cases or other problems that maybe someone can comment on.