All joking aside, what happened to the FIFO full terminal found when attempting to Write to a FPGA FIFO in 8.2?
LabVIEW 8.5 seems to remove this feature. I checked the error code too and it doesn't output an error if FIFO is full. Is there another way to check this other than assuming the fifo is full when the FIFO Write timeout?
Thanks,
Craig