Are there problems with doing PID calculations on FPGA?

[Richard2950]

I have an application that requires 8 PID loops operating at about 15 kHz. It would take two PXI-8176 controllers to do this with floating point calculations. One FPGA module could do it in plenty of time for a fraction of the cost, but the calculations would have to be done with integer math. Are there any serious pitfalls there? I don't really need the derivative gain at all, P and I are enough, but it seems that accumulated roundoff error in the integral might cause problems. Are there any techniques to deal with this?

[Stephan_A]

Hi,

you're right. There a certain things to keep in mind when dealing with integer based math on a FPGA. Below you can find some references and links I've found on the web by searching Google. Hope this helps:

References:
(1) Murphree, Jerry & Brzezinski, Brent & Parker, Joey K., (2002). Using a Fixed-Point Digital Signal Processor as a PID Controller, Proceedings of the 2002 American Society for Engineering Education Annual Conference & Exposition. (emsyl.ece.ua.edu/murphree/Linact%20Web%20Page/ 2002-1645.pdf )

(2) Feedback Control of Dynamic System, 3rd Edition by Gene F. Franklin, J. David Powell and Abbas Emami-Naeini Published by Addison Wesley

Links:

Continuous-Time Signals and Systems
http://zone.ni.com/devzone/conceptd.nsf/webmain/A907
9524FB29D67986256D7B0079E2FD?opendocument
Using a PID-based Technique
For Competitive Odometry and Dead-Reckoning
http://www.seattlerobotics.org/encoder/200108/using_a_pid.html

Regards

Stephan A.