Hello, I need to fix an architecture for the implementation on cRIO. My current operation involves 1:Flushing out elements from the FPGA to RT DMA FIFO when the number of elements remaining in the FIFO are approximately 60,000 2:My second loop on the cRIO does processing of each element using a For loop and when the number of elements satisfying the processing criteria are greater than or equal to ten I need to transmit it using Network Streams . This is my current requirement. 3:I am using Queue to transmit buffered data from the first loop to the second loop. My observation: 1:The first loop executes pretty quickly while the second loop involves processing and is a lot slower compared to the first loop . As a result, I am able to transmit very few data points on my PC after which the VI on the cRIO stops automatically. I guess the reason for such a kind of behaviour is probably the Queue is filling up much faster than it is getting emptied due to the slow processing speed. I need an efficient Architecture which handles such kind of memory constraints. Could anyone please propose an efficient Architecture for handling this? Thanks.

Right-click on the array constant to the left. There should be an option to set the array size. Also, remember that arrays in an FPGA must be a fixed size. Therefore you need to use Replace Array Subset instead of Build Array.

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Best architecture for cRIO implementation

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Hi,

Thanks a lot for your input the issue with the array is now fixed after I tried it with your suggestions 🙂 .

Thanks once again.

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Best architecture for cRIO implementation

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