03-14-2017 02:13 AM
Hey all,
I got my answer in the beginning of this discussion - LabVIEW has limitations in the size of the block diagram and the front panel.
The rest of the discussion is just enjoying communication capabilities. The content of my VI is completely irrelevant to the topic of my discussion.
Thank you all for sharing your opinion and time!
Cheers,
Evita
03-14-2017 04:07 AM
natasftw wrote: Just because things CAN be more parallel on FPGA doesn't mean they SHOULD be.
Statement is completely true. Luckily this is NI LV and not the high performance signal processing forum 🙂
Kind regards ~
03-14-2017 09:58 AM
@VUC wrote:
The rest of the discussion is just enjoying communication capabilities. The content of my VI is completely irrelevant to the topic of my discussion.
Well, the gist of the question is not "How do I make a block diagram work even if it exceeds the size limits", but "How do I sort a fixed size array on FPGA".
We tent to boil down convoluted questions to the core of the problem, and I think we did here. 😄 The rest is up to you....
03-15-2017 01:53 AM - edited 03-15-2017 01:54 AM
@altenbach wrote:
@VUC wrote:
The rest of the discussion is just enjoying communication capabilities. The content of my VI is completely irrelevant to the topic of my discussion.
Well, the gist of the question is not "How do I make a block diagram work even if it exceeds the size limits", but "How do I sort a fixed size array on FPGA".
We tent to boil down convoluted questions to the core of the problem, and I think we did here. 😄 The rest is up to you....
Instead of this array sorting could be anything else even bigger, then another environment might be chosen.
03-15-2017 10:36 AM
@VUC wrote:
ad of this array sorting could be anything else even bigger, then another environment might be chosen.
Yes, one can write bad code in any language, of course. I am not sure if there is an upper limit in the number of lines in VHDL, but I am not trying to do the experiment.
LabVIEW often compares favorably. 😄
03-15-2017 03:12 PM
@altenbach wrote:
LabVIEW often compares favorably. 😄
Yes, LabVIEW FPGA compares favorably for most cases. But not for the case for what FPGAs are made for: https://motherboard.vice.com/en_us/article/intel-bets-167-billion-on-the-massively-parallel-future
Unluckily LabVIEW FPGA lacks the VHDL most powerful statement - GENERATE statement that allows instance well connected thousands of counters (or anything else) in 3 lines of VHDL text.
Similar feature of LabVIEW - scripting does not help here. Of course, other languages (VHDL) must be used.
03-15-2017 05:22 PM
@Acaps wrote:
Unluckily LabVIEW FPGA lacks the VHDL most powerful statement - GENERATE statement that allows instance well connected thousands of counters (or anything else) in 3 lines of VHDL text.
Well, sometimes you could just use a LabVIEW FOR loop and use the FPGA IP builder features to unroll it. It might even work on my suggested sort code above, who knows?
03-16-2017 03:20 AM
@altenbach wrote:
[...] Also getting the size belongs outside the loop (well the compiler will probably do it, but still.... ;))
Oooops. There you are definitely right!
Here's my quick attempt. Would be equally easy to use the IPE, of course.
This is essentially the other algorithm i linked. As stated, that algorithm performs better if there are many swappings to do during sorting. However, as you don't check if no swaps occur anymore during the sort, it will always run its total iterations. In the case that no swaps are done anymore, my algorithm terminates.
Which one performs better overall?
I am not the correct person to tell as my statistic capabilities are... limited 😄
03-16-2017 11:00 AM
@Norbert_B wrote:
This is essentially the other algorithm i linked. As stated, that algorithm performs better if there are many swappings to do during sorting. However, as you don't check if no swaps occur anymore during the sort, it will always run its total iterations. In the case that no swaps are done anymore, my algorithm terminates.
Which one performs better overall?
I am not the correct person to tell as my statistic capabilities are... limited 😄
Good question. I don't know either.
Depends on the relative costs of the comparison and swap operation, and it also depends how the Min&Max is implemented. If it is done right the inputs and outputs are in place and the swap occurs only if needed, so it is probably not that different. Who knows?
Sometimes, as the Nike commercials tell us, just "do it" is cheaper than to first determine if it should be done or not. 😄
Also, a fixed number of iterations can probably be more easily unrolled into the FPGA fabric, Yes, your code stops early, but seems to run one extra iteration where no swap occurs. so it is not that early. It helps most if the array is nearly sorted in a certain way. Since my inner iterations get shorter and shorter, stopping early saves less and less work overall, while your checking for conditional termination is not free either. 😮
Would be interesting to explore, except that there are much better sorting algorithms to begin with. 😄