Block Memory Generator

[cwms]

I've been trying to use a sual-port block ram generated by the Xilinx Coregen tool in LabVIEW, but I can't seem to get data to write to it. I think part of my problem is on the second screen of the "Block Memory Generator 3.3 Node Properties" I am confused as to the settings I should select for the clock signal and IP enable signals. It doesn't make sense to me the selection of options I have for the IP Enable signal...and I suppose I'm not exactly sure what the IP enable signal is for either, since it seems like the write enable signals for inputs A & B should handle that. If someone can shed some light on the proper way to configure the dual-port block RAM, I would be greatful. Thanks.

[Thør]

The IP enable signal will act as a global enable, where the write enable signals will enable or disable either A or B individually.  What are your options for your IP enable signal, and what selections can you make?  An IP enable signal always tied true should behave as if it's not present at all, so that might be an option for you if none of the selections allow you to not specify an enable signal.  I hope this helps, and let me know if there's anything I missed.