Can HDL Nodes be buried in subVIs?

[jayde]

Is it permissible to bury an HDL node into a subVI?  I tried this, but am seeing an oscillation at the output.  Could it be that the enable is repeatedly being deasserted due to an input (such as reset) asserting?

The enable control is included as a process in the HDL node (as per an NI app-note), and I run the HDL node with "single cycle timed loop not allowed". 

When I include the HDL node in the top level of the FPGA-VI, it works as per the design.  When I bury it in a subVI, it seems to oscillate when attempting to output a logic high (a pattern of ~140ns off/1us on).

Is there a property that should be assigned to the subVI in order to make this work?  Or should I just not use subVIs with HDL nodes?

Another related question arises:  can one embed a complex hierarchal VHDL design into one HDL node?  Currently I'm using individual modules and connecting them together in the LabView Block Diagram.  But could I put the whole top level VHDL design (consisiting of a list of components, and their associated wiring) into the HDL node as long as I include all the relevant VHDL files using the external file tab?

Thanks,

Jayde

[jayde]

The latest findings:

I thought perhaps that I should put an infinite while loop around my subVI and that this would fix the problem.  However, after I inserted the while loop in the subVI, another part of my design (the DAC outputs) stopped working.

What happens if I don't have the while loop in the subVI, even though the calling VI is running continuously? (Both are FPGA based VIs.)

I used the calling default on the subVI (load with callers).  Should I be using "Load and retain on first call"?

If anyone has any insights or pointers, I'd be most grateful.

Thanks,
Jayde

[Yi Y]

Hi Jayde,

Yes, you can include as many VHDL files as you want with the HDL node under the code and external files node. Please refer to the "Importing HDL Code into FPGA VIs (FPGA Module)" in LabVIEW Help on how to do it.
You should be able to bury HDL nodes in a subVI.  I'm not sure exactly why you are seeing the oscillation, but if you could post the minimum amount of code and the hardware you are using, I can try to reproduce what you are seeing, and give you some pointers as to what's causing it, or report it if it's a reproducible bug.
If your subVI is being continuously called by your calling which is in a loop, it should be called every time the calling VI calls the subVI, the subVI will execute.  Try to check to make sure that the output line is not being reset anywhere else in your code to cause the oscillation to happen.
It shouldn't matter which setting to choose for the subVI, either load with callers or load and retain on first call.  It's the same in FPGA.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

[jayde]

Yi,

Thanks for commenting on this.  I'm in a total funk.

I tried to combine most of my design into one hierarchal HDL node, and in concept this should solve my problem.  However, when the compiler runs, the following error occurs:

ERROR:Xst:528 - Multi-source in Unit <hdlnode1> on signal <SYNCYP>    Sources are:    Signal <mytop/n_273/n_233/hdlnode1x/HM/BB/currState/Out18> is assigned to logic    Signal <mytop/n_273/n_233/hdlnode1x/HM/BB/currState/Out17> is assigned to logic CPU : 223.89 / 224.00 s | Elapsed : 224.00 / 224.00 s

This is particularly frustrating because the same design compiles flawlessly when implemented using the Xilinx tools. 

I removed all the top level connections to make sure nothing was interfering with the SYNCYP output.

Have you ever seen this synthesis error using the HDL nodes?

I even went into the "BB" component and tried to change the line that generates SYNCYP -- now it reads SYNCYP <= '1'; but I still get the same error.

Since the same hierarchy synthesizes using Xilinx tools, what can be wrong?

I'm going back to the subVI version and I'll try to work the design out that way.  I'm posting the design (which is fairly simple).   The FPGA VIs are the ones to look at.  The full HDL node version is labeled as such -- uses the same HDL code as the other FPGA VI.  If you look at the decentralized version, you'll see why I was trying to use the subVIs -- there's a lot of repetition.  Does it look like the subVIs are set up correctly (i.e. no need for an internal while loop, because the main FPGA VI has one...)?

Thanks again,

Jayde

[jayde]

One comment about the previous message:

in the posted FPGA-VI containing the subVI implementation:  DIO10 should have the same shape as DIO6. 

However, DIO10, the SDFBP-Y signal oscillates at a much higher frequency.

DIO6 is the correct signal.

Both modules are the same HDL code and stimulus, but the DIO10 version has the HDL node buried in a subVI. 

[Yi Y]

Hi Jayde,
I'm going to try compiling your file on LabVIEW 8.5 and see if the same error occurs.  It's possible that this is one of the bugs that is fixed in the newer version of LabVIEW, but I'm not sure until I test it out.  I'll get back to you with my results.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

[Yi Y]

Hi Jayde,
I tried compiling your project in LabVIEW 8.2.1, and I was able to get a successful compile.  It's possibly because I have LabVIEW FPGA 8.5 installed and maybe some of the shared files contained the bug fix.  I will attempt again to compile on a machine that does not have 8.5 and see the result I get.  However, at this point, I think it's probably a known issue that's fixed in 8.5, and an upgrade will probably fix your problem.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

[Yi Y]

Hi Jayde,
I had my co-worker who does not have FPGA 8.5 installed compile your project and his compilation failed.  This issue seems to see improvement with the installation of 8.5.  Hope this information helps!

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support

Message Edited by Yi Y on 08-15-2007 05:43 PM

[jayde]

Yi,

I've been out of the lab for a while, but should be able to work on it tomorrow and Friday.

My next step will be to upgrade the software installation. 

Jayde

[jayde]

Latest installment:  I downloaded and upgraded to to LabView 8.5.  However, when I attempt to run the FPGA VI, I get an error.  Apparently I need a version of LabVIEW FPGA that supports 8.5. 

In the meantime, I'll try to get one of my three versions of the FPGA VI to run correctly under 8.2...

Jayde