As a matter of fact, I did use 80Mhz to oversample 5M signal.
The thing is, if we are talking about fpga tick, we'll usually do it in a SCTL, make sure the job can be done in just one tick, so a for loop is not allowed.
I did try IPgen toolkit to convent for loop to make it effectively run in FPGA, the result is yes we can have such IP core running, but I will have 500 tick or so latch.
Divide the for loop to many 8bit array isn't help, the latch would pretty much the same.
I would accept latchs in most time, but in this application I need to trig external device to capture communication, If I only need to decode frame itself I wouldn't think that a big problem, only make same amount of sample in shifting registers would solve the problem.
