Can LabVIEW FPGA IP Export support Zynq UltraScale+ MPSoC?

[sz.benjamin]

Hi,

I am really interesting to use my mathematic algorithms from my old Zynq-7020 SoC based sbRIO in a new Xilinx Zynq UltraScale+ MPSoC. Is it possible to generate VHDL for Zynq UltraScale+ targets via LabVIEW FPGA IP Export Utility?

[Terry_ALE]

The documentation says the FPGA must be from the same family.  That said I have seen this get stretched if the functions being used are not too specific.

[sz.benjamin]

I am using High Throughput Math Functions for example: Complex Multiply, Rectangular to Polar, Square Root, Multiply, Add for 16 bits fixed-point datas/numbers and some z^-k delay boxes. Aren't these too specific yet?

[Terry_ALE]

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@sz.benjamin wrote:

I am using High Throughput Math Functions for example: Complex Multiply, Rectangular to Polar, Square Root, Multiply, Add for 16 bits fixed point numbers and some z^-k delay boxes. Aren't these too specific yet?

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Maybe try a proof of concept using the evaluation mode of this add-on.  Make a VI with just one of these functions and see how it exports and can then be imported.  Do you have VHDL/Vivado expertise?

[sz.benjamin]

I have strong experiences in Vivado block design making and using them on AXI bus with Linux kernel drivers, but i have much less in VHDL coding.

[Terry_ALE]

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@sz.benjamin wrote:

I have strong experiences in Vivado block design making and using them on AXI bus with Linux kernel drivers, but i have much less in VHDL coding.

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Then definitely worth a shot.