Can Vivado HLS IP blocks be added into LabVIEW FPGA?

[Terry_ALE]

Could a Vivado HLS block (e.g. https://www.xilinx.com/support/answers/55279.html) be added via a CLIP or IP Integration node to LabVIEW FPGA?

[DonhJoe]

Hi,

Is there a way you can get a VHDL file for that implementation?

Regards,