Can a period timeout be used as a hardware trigger

[fr@nk]

I'm trying to read a 20 bit word in SSI protocol and can't get the required timing.

I'm using a Labview 2011 (not RT) and a PXI rack with an M series PXI-6251 DAQ board to generate a clock signal at 100Khz. The clocks negative edge is the sample clock to input the SSI data into an array. The interface runs in a 100mS loop to set up the message period. This works fine.

Now I have to read the same SSI message where the clock is generated externally so I need to input the clock and use it as a sample clock to collect the data. The problem is that the intermessage gap is 45uS, followed by twenty one 100 Khz, 50% duty cycle clocks. This is repeated continuously. I need the 45uS interval to trigger the data collection but can't get the inter message gap to start the clock/ sample process in a timely manner.  Top level VI is SSI_Sim.

Thanks

Frank

[Jason-M]

fr@nk,

Let me just clarify a few things:

Based on the supplied code, you are attempting to read a single floating point sample from a Counter input task. When this input has a pulse width of 35 us, you want to move onto read a digital 8 bit line for 20 samples, process this data, and then close the program. Is this correct? I don't know if this is the exact thing you want to see though, based on your description, you would prefer to the counter to count up to a value equivalent of 45 us based on the clock rate, and then you want to read the digital signal? So essentially the counter task only acts as a delay? It makes sense that you are not seeing this now, since you have a lot of software delays, such as nested loops, flat sequence structures, and nested loops with the logic.

Perhaps this example does more what you were looking to do:

Count Digital Events with a Pause Trigger

Also, here is some more information on setting up a trigger delay:

Delay Between Trigger and First Sample on M Series, X Series, and E Series Multifunction DAQ

Best,