Can't seem to measure above 1k S/s, please help

[TomSegal]

Hello,

thank you for your help.

I created another labview project using the FPGA wizard for a DMA engine, and with that project I can only sample as high as 500k instead of 750k, even though I did not modify the generated project in any way - I didn't make it so that it saves into a file or anything else.

When using these settings:

 number of scans: 600000, loop rate: 530000,

I get buffer underflow. Only when reducing the loop rate to about 520000 do I stop getting buffer underflow.

What am I doing wrong?

(see attached)

Thanks!

[Norbert_B]

What is the loop rate configured to?

When i execute the FPGA Wizard and select 600kHz, the loop rate is configured to 67 Ticks. Opening your FPGA vi says something of '1'.

hope this helps,

Norbert

[TomSegal]

When I create the project via the FPGA wizard, I select 750k for the rate. I then click generate files and I get fpga.vi and host.vi.

In the host.vi I type in: loop rate 750000, sample rate 1000. It then goes into buffer underflow. Only when I reduce the loop rate value to 500000 or below it doesn't go into buffer underflow.

As far as I understand you were referring to the FPGA.vi. Must I use the FPGA.vi? I'd rather use the host seeing how I don't have to recompile every time that way.

[Norbert_B]

The host VI is only the interface for you to interact with the (running) FPGA VI.

So when starting the Host VI, there is a function called "FrequencyCoercion.vi". It takes the requested sample rate and coerces it to a value manageable by the FPGA.

If you configure 600kHz, it should return 67.

If you go for 750kHz, it should return 53.

This is passed to the FPGA VI before it is started (same node in Host VI). Your FPGA VI has a default value of 1 in this, so the FPGA would try to run AI with 40MHz (default clock). Naturally, AI is not that fast, so a buffer underflow is an expected error.

hope this helps,

Norbert

[TomSegal]

Thanks for the explanation.

When I select loop rate 750000 and sample rate 1000 and click play in the host.vi, the fpga.vi updates with a tick rate of 53. I still get buffer underflow though.

[Norbert_B]

"sample rate", as you call it, is the "Number of Scans 0" control of the host VI?

You can try to use different configurations with Loop Rate/Number of Samples, but it seems that the FPGA code created by the Wizard is simply not performant enough.

You can implement your own FPGA VI and it should contain "pipelining" for parallising DMA buffer access and DAQ reading. See this example:

hope this helps,

Norbert

[TomSegal]

I tried recreating it but I'm a bit amaturish, could you please attach the actual file?

It is for the FPGA right? The host.vi remains the same?

Thanks!

[Norbert_B]

This would imply a complete rewriting of the FPGA VI.

The host VI could stay the same given that you rebuild the mechanisms of communication between FPGA and host (DMA and controls on FPGA VI).

The screenshot only shows the algorithm for reading the AI and storing the data (next iteration because of pipelining) into the DMA. So its really only an excerpt.

I didn't implement this example myself but only have this screenshot. So i am sorry that i cannot provide any code on this.

Norbert

[TomSegal]

Okay

So basically you're saying that the DMA program automatically generated by matlab is not performant enough to arrive at 750k? Is there maybe a different template that I can base my program upon which is more performant? Or perhaps a tutorial showing how to arrive at one, such as the one in the picture you posted?

Thanks

[Norbert_B]

Tom,

i understand your phrase "matlab" in this context as an error during writing 😉

Well, i haven't done any tests with hardware. But since you state that the buffer underflows, the acquisition loop has to run too slow. That means (esp. since slower rates are possible as you tell us) that the current implementation which is done by the FPGA Wizard is not performant enough.

Nevertheless, you can take the code from the Wizard and change it as such that it "matches your requirements".

Gaining the knowledge for this is possible by:

- Attend the LV FPGA class from NI

- This tutorial might give you some new information

- This tutorial answers the question: what is pipelining and what do i gain with it?

-...

Gaining expertise for implementation can only be achieved by actually "doing it" 😉

hope this helps,

Norbert