LabVIEW
Channel Wires on RT systems, duplicate VI error
Bob,
I just made a test as well and it does not show this error. The tag is from one loop running entirely on the RT remote cRIO system. The error is in building the "Source Distribution" and not in the actual execution. BTW, in looking on the RT system I can't find anything that remotely looks like a renamed VI. The "initialize.vi" is in the folder for the tag and nowhere else. I just deleted my "build" folder and rebuilt everything and the error still shows up for that one Source Package.
Here is my test VI diagram that behaves as expected and builds with no errors. And then the much more complicated actual RT diagram that shows the error every time it builds. Though it seems to run correctly. As you can see I have one queue and one channel wire. I have been considering replacing the queue with a second channel wire but error is making me nervous. I use the tag since I just want the server to show the current value at a much lower rate than the high speed raw data stream that is saved only in certain trigger cases.
@Bob_Schor wrote:
@sth wrote:
The error is in building the "Source Distribution" and not in the actual execution.
Hmm. Could that be the problem? Can you see if you can build an Application (.exe)? Maybe if it sees a "Source Distribution", it thinks it may need something from ExtraVILib ...
Bob "Grasping at Straws" Schor
That is great straw. It is a problem with building a "Source Distribution". For some reason it seems to think that the Initialize.vi is needed twice and renames one instance. Except that I can't find what it renames it to. Also it is only needed once. My guess is that this is a bug in the Application Builder that does the resolving. This warning comes up almost immediately when building the Source Distribution so is part of the first phase of getting the list of files.
I can't recreate it from a simple test, so I will take my large project and start deleting things until it goes away.
I started stripping down the code and the error goes away when I removed all the references to accessing the FPGA!!! I am not sure what this means, and when I did that I did remove a lot of the code but nothing to do with channels.
I put a FIFO read from the FPGA to the RT system and the build threw the error. This is just weird.
I thought that channel wires would be my next "big thing" for me, but I found them disappointingly fraught with unnecessary tension. (I renamed a typedef and suddenly I cannot regenerate the channels.)
Plus, now I have channel wires running around in different directions, implying data flow but not actually BEING part of the data flow. I'd much rather have the "spooky action at a distance" of a queue captured in an A/E or global.
The first issue was the thing that got me, though.
If you rename a typedef I think it would need to regenerate the channel code. This did get confused on early versions of the channel creating code. HOWEVER, you can go to your LabVIEW Data folder and delete all the channel code. It is in <labview version>/ExtraVILib/ChannelInstances and there is a folder and a lvlib for each type of channel.
If you rename a channel but changing the typedef outside of LV project, it can get confused. It should work within the project.
To me, I have the channel wire and so is not spooky action at a distance but more "out of band" communication between sections of a program. I find a better graphical visualization than a queue where you have to trace it upstream to the creator and then back downstream to the consumer to figure out where your data is going. Channels are just a nice straight connection between the two points on the diagram.
If you start using FPGA programming you will have FIFOs popping up all over the place and they are essentially the same thing, but it is nice that you have graphical connection between them rather than just hunting for the name. Of course channels don't work on FPGA (yet) but it would be a nice addition.
Lastly, the error above that started this thread, is due to use of a FIFO from the FPGA to the RT system. That seems to be the name conflict!
@sth wrote:
If you rename a typedef I think it would need to regenerate the channel code. This did get confused on early versions of the channel creating code. HOWEVER, you can go to your LabVIEW Data folder and delete all the channel code. It is in <labview version>/ExtraVILib/ChannelInstances and there is a folder and a lvlib for each type of channel.
If you rename a channel but changing the typedef outside of LV project, it can get confused. It should work within the project.
To me, I have the channel wire and so is not spooky action at a distance but more "out of band" communication between sections of a program. I find a better graphical visualization than a queue where you have to trace it upstream to the creator and then back downstream to the consumer to figure out where your data is going. Channels are just a nice straight connection between the two points on the diagram.
If you start using FPGA programming you will have FIFOs popping up all over the place and they are essentially the same thing, but it is nice that you have graphical connection between them rather than just hunting for the name. Of course channels don't work on FPGA (yet) but it would be a nice addition.
Lastly, the error above that started this thread, is due to use of a FIFO from the FPGA to the RT system. That seems to be the name conflict!
Yes, I tried to get it to manually regenerate by deleting the folder you mentioned above (while LV is closed), then opening the project. Onle some of them regenerated, not all. I also tried all of the things that Bob mentioned in various threads (I follow all of his posts on channel wires because I consider AQ to be the technical expert and Bob to be the practical one). The problem is, I should be able to fix this problem; I just can't.
Hmmm, I wonder if this is one of those cases that Bob was talking about in another thread re: renaming typedefs?
