05-20-2025 01:39 AM
Dear Users,
For, myRIO1900 - Connector A/AI0
Reference : https://www.ni.com/docs/en-US/bundle/labview-myrio-toolkit/page/myriohelp/myrio_one_sample_n_samples...
Hardware-timed acquisition—The FPGA target on the myRIO has a 40 MHz clock rate, which controls the rate of acquisition. The sample rate depends on the hardware clock, which is faster than a software loop.
Buffered acquisition—FPGA transfers the samples from the FPGA target to an intermediate memory buffer using direct memory access (DMA) before LabVIEW reads these samples on the real-time processor.
My question is, Does the above statement applicable for FPGA also ? (i.e. When I use FPGA I/O Node [Connector A/AI0] in FPGA for acquiring high speed signal). Because I don't find any option to configure AI as 1 sample / N samples. Or by default, will It take as N Samples?.
Can anyone please clarify my doubt about Connector A/AI0(1 sample / N samples)?
05-20-2025 03:43 AM
On FPGA you simply read the IO node value which is always a single sample. Your acquisition must be done in the FPGA code inside a loop and you can then either build an array (not recommended on FPGA in most cases) or send the value to a DMA FIFO to read the values sufficiently fast as an array in the real-time part.