Hello all
I am somewhat new to LabView FPGA/RT and am having a hard time understanding the logic behind this NI provided code. Here is the original source: http://www.ni.com/example/30984/en/.
I have come to the conclusion that the following process occurs. If anyone could check my understanding it would be appreciated.
My understanding of the logic behind the code:
1) The RT VI uses a Read/Write control to write the user inputs (Enable RT Watchdog, RT Reset on Watchdog Failure?, and RT Timeout Period) to the FPGA.
2) The RT VI reads the current state of the output modules (these are stored in an array called "Analog Control Inputs" along with separate boolean inputs labeled DI1, DI2, and DI3.
3) Using user entered parameters, the RT VI uses a PID controller to gradually ramp the current value of the output modules (Analog Control Inputs and DI1, DI2, and DI3 which were read from the FPGA VI) to the user entered set points.
4) The output of the PID controller is then sent to the FPGA via a Read/Write control (the explicit names are "Analog Output Control" which are the new values the Analog Output modules are to output), the new values for all the boolean values are sent as well, and, assuming the process ran correctly, the "Pet RT Watchdog" and "RT Safe" variables are set to the appropriate values to indicate to the FPGA everything went according to plan.
On the FPGA side:
1) Both input loops take the current state of the C-Series output Modules and store them to the front panel indicators which are read in from the RT VI. The loops see what value they are currently outputting.
2) The Output loop waits the given update period, then feeds the appropriate values into the C-Series Output Modules (either the programmatically defined safe state [active during the "Safe State" option] or the user entered values [active during the "Normal Operation" option]). This changes the C-Series output values to the programmatically defined safe state or the user entered values. The Output loop then tests to see if it should go into Safe State or Normal Operation and carries that over to the next iteration of the loop.
3) The RT Watchdog loop monitors the RT software watchdog. If "Enable RT Watchdog" is true, it checks to make sure the time between pets of the RT watchdog occur within the user entered time interval. If a time out occurs, the "Watchdog Safe" variable is set to false, effectively indicating the Output loop to activate "Safe State". Finally, the RT System is reset if the user set "RT Reset on Watchdog Failure" as true.
Thank you to all who read this far!
