Coding cRIO 9402 DIO on FPGA

[Pete.Dunc]

Hi guys,

I am writing an application for the following hardware;

Controller - cRIO 9022

Chassis - cRIO 9114

Modules - 9402 DIO, 9213 Thermocouple I/P, 9205 AI

The 9213 and 9205 are both taking low frequency measurements so I plan using the scan interface for these modules.

One channel of the 9402 will be required to determine the frequency of a digital signal at ~4 MHz so I will have to code this using the FPGA interface.  Two other channels will be required to output low frequency digital signals.

I have looked at the Count and Period (FPGA) example in the example finder;

• In my application, instead of generating the pulse train, would the 'Digital Signal' in the timed loop be replaced with an I/O node?  And the While Loop removed?
• How could I expand this to write Boolean values (communicated from the host vi) to 2 other outputs?

I have read the cRIO Developers Guide which uses DMA FIFOs to communicate between Host and FPGA, would I require multiple DMA FIFOs?  This is the first application I have written for a cRIO target so any and all tips/references are appreciated

Many thanks,

Pete

[DBerry]

Pete,

I think you are on the right track...the CRIO developers guids is a good source for info.  As far as Scan Engine vs FPGA, since you need the FPGA performance for your high Frequency measurements, I would recommend writing all of the code for FPGA (no Scna Engine).  There is a "hybrid" mode that allows you to setup the CRIO to be a mix of FPGA and Scan Engine but I believe there are some limitations.  I think you will get better perfomance without running into any pitfalls if you run full FPGA. It will also allow much more flexibility in your application w/o too much more effort.

To answer the questions:

1. You can get rid of teh pulse train loop from the example.  The "Digital Signal" will be replaced by yur FPGA IO node for the 9402.

2. In full FPGA you will have access to 3 DMA FIFOs.  You can use separate FIFOs for each acquisiton module or you can interleave data from multipl channels/devices as long as teh data type is consistent among all. I can't speak on performance variation between the two options, but there is some info out there on interleaving that should help:

http://decibel.ni.com/content/docs/DOC-15034

http://decibel.ni.com/content/docs/DOC-6303

3. For boolean outputs from Host: You can write directly from your host VI (e.g. Windows LV app) using an FPGA write node.  As long as you are not trying to stream arrays of data this should be fine.  For example, if you just want to have a UI boolean control a channel on a DO module you can use this method.  Your FPGA code will also need a corresponding boolean wired to an FPGA IO node configured for the respective channel.

Hope this helps.

Dan

[Pete.Dunc]

Hi Dan,

Thank you for the reply.

• I was planning on running in Hybrid Mode as you mentioned, although you're probably right that coding straight to the FPGA will avoid some hiccups.
• I will interleave the analogue inputs and thermocouple inputs as these are both measurements taken at similar frequencies.

I had a quick go at making a host and FPGA VI to the analogue inputs from the AI and Thermo modules;

FPGA.vi

Host.vi

This doesn't run at the moment but I think it's because I'm simulating the hardware, as it arrives early next week.  I still have a couple of questions about how to expand this to include the digital module.

• If I want a 'Digital Acquisition' loop to run on the FPGA at a different sample rate to I just make another loop with a lower 'Data Rate' constant?
• How would I then read from the new DMA FIFO on the host VI?

I think the reason I am having trouble is that I can't find examples which have multiple IO running on the FPGA at different sample rates.

Thanks again,

Pete

[Pete.Dunc]

For example;

[DBerry]

Pete,

What you've done here looks fine.  You can run two parallel loops to get your different data rates.  An alternative would be to utilize the same loop and do some iteration checking so as to write to the boolean at the different rate.  For example, in the case you show here, it looks like the second loop only needs to run 1/2 the speed of the first.  So you could just execute that code inside the first loop on every other iteration.

Writing to an indicator in the case of the DI loop (Mod3/DI0) is also fine here, as long as you don't need to worry about losing any samples on the host side.  I am guessing this is some sort of trigger/indication, etc.?  And in this case you don't need to use a second FIFO and can directly read the Mod3/DI0 indicator value on the host using an FPGA read node (not FIFO read).

If it turns out you need to buffer the digital data with a second FIFO then reading this FIFO will be the same as for the first and can be done in the same loop on the host as shown for the first.  Just configure the FIFO read to poitn to the other FIFO.  

Just a note:  It seems that you are leaning towards full FPGA rather than hybrid, but if you end up with the hybrid mode, the Scan Engine uses 2 of th three available DMA FIFOS so you will only have one to work with in your FPGA code.

Dan

[Pete.Dunc]

Dan,

Ideally I would be looking for 3 different sample rates ('fast' for digital I/O, 'medium' for AI and 'slow' for thermocouple inputs) so I have tried to use your alternative method;

The timescales here are arbitrary, but the concept seems to be working.

• Losing some samples from the AI and Thermocouple inputs will not be greatly significant so I will use the FPGA read on their indicators as you suggested.  Should I covert to U32 in their respective case structures?
• The 'Digital Input' indicator will be replaced with the logic to calculate the frequency of the signal and a DMA FIFO will transfer the frequency values to the host.  This part of the application is to measure the variation in frequency of a 2 MHz TTL wave.
• I have noticed that 'Acq Loop Ticks' fluctuates 8,000,000 +- 40,000, could this be as I'm simulating it on the dev machine?

Getting there!

Pete

[DBerry]

Pete,

Looks good...nice and neat code!  

I guess I wouldn't convert the FXP data to U32 in the FPGA code unless you needed tp transfer via FIFO or use some function (IP block) requiring a U32 as input.  Keeping as FXP will maintain the highest precision.

I believe you are correct that running in sim mode is causing the clock inaccuracy.  I have not used this mode but the HW clock should be very stable.

Dan

[Ashokan]

Hi dudes,

I need to write the codes for the following :

cRIO : 9025

Modules : 9229 (3 modules; total 12 channels)

It has to acquire the data @ 50ksps simulatenously and to store the data.

Can any one help me... Please..

Thanks & Regards

--Ashokan

ashok3085@gmail.com