Compilation problem for NI 5781

[Malik_gul]

Hi,

I am trying to use NI 5781 with system non-synchronous CLIP with PXI triggers but I get the following compilation error.

ERROR:Place:905 - Components driven by Regional clock net <IoModClipClock0>
   can't be placed and routed because location constraints are causing the clock
   region rules to be violated. Regional Clock net <IoModClipClock0> is being
   driven by BUFR <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni5781Basex/AdcDcoBufr>
   locked to site "BUFR_X0Y5" Because of this location contraint,
   <IoModClipClock0> can only drive clock regions "CLOCKREGION_X0Y3,
   CLOCKREGION_X0Y2, CLOCKREGION_X0Y1". The following components driven by
   <IoModClipClock0> have been locked to sites outside of these clock regions:
   Puma20Window/theVI/aLvTrig1_din/cFirstRegister_ms (Locked Site: ILOGIC_X1Y198
   CLOCKREGION_X0Y4)

I have attached a simple example project. I am using a trigger line to start reading from AI0 and AI1 pins of 5781 and put the data in a T2H FIFO. The host controls the trigger value and the FPGA VI reads the trigger in the SCTL driven by "IOModuleclock0". The CLIP for 5781 is ver 1.1.0 non-system synchronous. I do not want to use the system synchronous CLIP as it will change the sampling frequency to 100 MHz instead of 50 MHz and I will have to change a lot of things in my design. Interestingly, if I remove the trigger from the SCTL driven by "IOModulclock0", the compile passes.

Can you kindly check the attached project to see if there is any problem in the configuration of 5781. I set the "IOModuleclock0" to 50 MHz.  Any help will be greatly appreciated.

Regards,

Malik

[Branch_Support-NIC]

Hi Malik,

Thank you for posting. The compilation issue that you are experiencing when trying to compile your code is a known issue with LabVIEW. This unexpected behavior has been documented by R&D in CAR #236803. As you explained in your post, one workaround for this issue is to read the trigger lines in anoter clock domain and share the data through global variables.

Best Regards,

Allison M.

Applications Engineer

National Instruments

[Malik_gul]

Thank you for the reply.

Actually I am trying to synchronize the sampling instants of two FPGAs within the same chassis using triggers. Can you tell give me an idea of the latency involved, if I use global variable.

Precisely, I am using a trigger line which is set by a master FPGA and the slaves listen to it and start reading from the 5781 once they get the trigger. The time difference in trigger arrival for different slave FPGA, as far is I know, should be in micro seconds

As suggested by you, if I read the trigger in a, say 100 MHz, SCTL and pass it to global variable which is then read in the SCTL driven by IOmoduleclock0, can you give me a rough figure of the time jitter I may get in the global variable propagation from one SCTL to the other (in different slave FPGAs)?

Thank you in advance

Malik

[Allison_M]

Hi Malik,

Unfortunately it is very difficult to predict what the latency associated with the global variable in this case will be. The amount of jitter will change with each compilation and will also be dependent on the other functionalities that you include in your program. The best way to determine this would be to run some benchmarking specifications on the code that you develop for your application. 

Regards,