Basically whenever the FPGA and the host are communicating, you will experience traffic between the two. A write from the host will always correspond to a read on the FPGA and vice versa. Thus you cannot pinpoint traffic to either target.
Why is it that you are trying to reduce this communication? Have you seen adverse effects of congestion causing problems in your application? If so, I might suggest using DMA FIFOs to buffer some of this data such that reads and writes are less frequent but pass more data during an interaction. I hope this information is useful for you. Thanks,
Mike D.
National Instruments
Applications Engineer
