Hi all,
Here I have a Problem related to High speed data acquisition using PXI 6562 detailed as below.
Hardware Used :
Tektronix Logic Analyzer - Used for generation of LVDS data.(Simple Ramp pattern is generated)
SMA 2164 - Prototyping Board for Connecting Various Signal to PXI 6562.
PXI 6562 - For Data Acquisition at nearly 10 MHz
compact PCI Chasees Connected with Host PC.
SMA Cables.
Experiment Setup :
Data, Clock and Trigger Signal (LVDS) are generated from Logic Analyzer and connected to SMA 2164 via SMA Cables.
Data Signal - connected to Channel 0 of SMA 2164.
Trigger Signal - Connected to Channel 1 of SMA 2164
Clock Signal - Connected to Stobe of SMA 2164.
My purpose of experiment is to do full acquisition at external clock rate (10 MHz) and filtered acquired data
of channel 0 when channel 1 (trigger channel) is high . After that doing group of 8 bits of channel 0 and convert
it to numeric word, which should be ramp signal as generated.
Here what i am doing exactly (as attached in code - Dynamic Acquisition with External Sample Clock_old_QUEUE.vi)
After Configuration of card, i am start acquiring data by putting read vi in while loop and sending all acquired
data to queue. From another while loop, I unque that data and process it as per above requirement.
My post processing code after unqueing data is perfect.
Problem Facing :
I fected 1000 sAMPLE bunch continuously from read vi. Whatever 1000 sample i fected each time are of perfect
ramp pattern, although there is no synchronization in previous 1000 sample bunch ending and next sample 1000 bunch
starting data. means if my current 1000 sample bunch ends on 144 (decimal) then ideally next 1000 sample bunch
should start from 145 (decimal), but in recent condition it starts from say 130 or else. I couldn' understand
this problem as if data may be lost,then next bunch starting should be from greater then 145 or else.
For detailed understanding Herewith I have attached code.
One thing I want to mention is if i set bunch of sample to say 5000, then 5000 sample will have continuous ramp pattern
(in that bunch) but problem as detailed above remains same.
For Finite acquisition as attached in Dynamic Acquisition with External Sample Clock_Sequence Finder.vi Max sample lemgth
is 40000, till which i can get correct ramp pattern.
Please help me as soon as possible.
