Convention of passing clusters to VI's?

[F1_Fan]

Trying to figure out if what I did below is acceptable practice? I was annoyed with all the input / output wires so I built Type Defs for input and output. The type defs are specific to this particular VI so I have to unbundle a few clusters to populate the input cluster. It is repeated in reverse for the output. Please take a look at the picture below and give me an idea if I am way off base or not.

[Ray.R]

Hi,

It's a good start.  You can bundle everything inside a cluster.

Here is how I would do it.

1.  Leave the error cluster as it's own cluster.  Wire the Error In at the bottom left box of the connector pane & the Error Out at the bottom right.

2.  Leave the "Path to DANE directory" outside the cluster and wire it to the top left box of the connector pane. Path out would be connected to the top right.

3.  All other values (doubles and numeric) are okay within the cluster.  Wire the cluster to one of the middle boxes on the connector pane (depends on if it is an input or output <left - right>.

The above is based on a common practice where the error clusters are always placed at the bottom of the connector pane, paths and references at the top.  I usually use the 12 connector pane pattern.

RayR

[F1_Fan]

Based on the suggestions I made some changes.

I usually always put the error clusters in / out on the lower left / right corners but was trying to make the VI completely self contained based on one wire IO. I like the error clusters separate; and it does seem to be the correct convention. (What was I thinking.....)

I think I'm going to keep the path internal to the cluster because everything inside that VI (several sub vi's) depend on all that data being correct. It is also the only VI in the entire project to use that path.

I'm also getting my feet wet with LVOOP so I've been mixing concepts and doing my best to confuse myself 😉

New Image attached.

[Ben]

I make our rookies nervous when I walk apst their cubes because if I see something I don't like, I'll stop and comment. eventually they get their act together and I don't have to comment anymore.

So why am I telling you this?

Becuase if I saw this

 

when walking past I would stop to say...

"Nice Work!"

Ben

PS In my Type Def Nugget I mention using a sub-VI to hold the Type Def constant.

[Ray.R]

Looks good..

Near the bottom right corner of the Case Structure, there is a default tunnel.  What is that?  It's not a path, is it? 

If a boolean, what is it?  If it's to stop a loop, then it's probably alright.

(my eyesight is not what it used to be)

R

[F1_Fan]

It is a stop to the outside "while loop"; your only seeing one case of the QSM.

Thanks for the input; I'm still new at this labview stuff!

-Chris