03-19-2012 01:01 PM
Hello Fellow Developers:
I am using the convenient 9205 module on cDAQ chassis to acquire voltage differential signals, ultimately I’d like the following:
To get samples from 2 channels at 500Hz(min)/1kHz (preferred) with relative time stamp for every reading.
I was originally planning to get a time stamp before acquiring, acquire signal the samples, and queue the time stamp/2D voltage readings array to another loop for time stamp processing/data save. I was able to do a mock-up with DAQ mx, so far so good.
Santiago
03-19-2012 01:12 PM
To some extent it doesn't matter how much lag there is because your acquisition clocking is being done in HW on your DAQ board - not in LV. So yes the samples will be spaced exactly as they should (plus or minus the timing accuracy of the board, which is typically in the nanosecond range). Moreover, if you specify continuous sampling you can append the samples from one iteration directly to the end of the samples from the previous iteration because there was in actuality no gap between them.
Mike...
03-19-2012 01:23 PM
Thanks Mike for your prompt response. I will use continous then.
Since the HW is queueing 1000 samples every 1000ms, whereas I am pulling 1000 roughly every 1100ms, won't I eventually get data overflow? if so can you suggest a way to mitigate this?
03-19-2012 04:05 PM