DMA FIFO missing elements

[Harjot]

Hi all

I am using DMA FIFO architecture to transfer 5 channel data (NI 9222 input module) from FPGA to PC host. I am using cRIO 9014 controller in my application.

I have set the size of 1024 elements on the FPGA side. FPGA loop is executing at 500 kSamples/s (i.e. every 2 us)  On the host side (reading side) I am reading a big chunk of data e.g. for 17ms (No. of elements to read = 500KS/s*0.017*5(channels) = 42500).. But since this number is not exact multiple of 1024 so I defined the nearest multiple of 1024 (i.e. 43008) as the number of elements to read.. The total FIFO depth defined on the host side = 5*43008 = 215040 .

On the FPGA side the timeout is wired to "-1" so that FIFO waits indefinitely to write the data when the buffer gets full.

When I run my application I write the FIFO in a text file on the host computer. I see that everytime I run the VI I miss few data points which I thought is contributed to FIFO getting full. I tried to increase the size of FIFO on both FPGA and host side but it didn't solve the problem.

The most weired point I observed is that I am able to get continous data for the set reading size of 43008 elements and I miss exactly next 43008 elements This sequence repeats.

One of the reason I thought, might be  I am reading too many elements at once and this may be slowing down the execution of the reading loop resulting in a outcome that FPGA writes faster into the FIFO than host side reads.

I changed the number of elements to read to 3072 for time = 1.23ms.. The observation was I read 3072 elements and miss next 3072 elements.It seems that the data points that I miss are not dependent on the speed of reading loop but it is somehow linked directly to the defined number of elements to read.

I am stuck at this point and unable to solve this puzzle... Any sort of help in this regard will be highly appreciated.

[ToeCutter]

Please post your VIs.

[Sam_Sharp]

Why don't you use the property node that tells you number of elements in the FIFO and read that many?

[Harjot]

Please find the attached VI snapshots

Cheers 

Harjot

[crossrulz]

What's the point of changing your data from a double to a single and immediately change it to a double?  You are just causing memory allocations that are just not needed.

You could probably just get away with a Reshape Array instead of the Decimate and Build Array nodes.

The first thing I would try is to create a Producer/Consumer setup.  Move your file writing to the consumer loop.  This will allow your DMA read loop to run faster.

The next thing to try would be to check how many items are in the DMA.  Then use Quotient & Remainder to divide the number of samples available by the number of channels.  Multiply the Quotient by the number of channels.  Read this many items in the DMA and parse as needed.  This could allow you to read a lot more data in a single read and store all of the data.

[pepe70]

,..

[Harjot]

I used the producer consumer architecture by placing DMA read in the producer and passing  the data to queue. In the consumer loop, I am writing a text file on a flash memory target via cRIO USB port. The problem I detected with the code is my reading loop is still really slow and I see that the FIFO goes to overflow right at the time of first read. I am resetting the FIFO at start and I see that the FIFO gets full right at the time of first read. The other point I tried is to palce a check on the FPGA side DMA writing node to see if the host is ready. (as suggested in http://goo.gl/aLw6lo) .. Unfortunately this didn't solve the problem of FIFO overflow.. I tried to get the speed of the Reading loop by using the tick count (ms) function and shift registers .. I get the speed of reading loop (On RT) in seconds (30s-40s) which is way too slow ....I wonder how I can make the reading loop (on RT) run faster to avoid the overflow....

[crossrulz]

Can you show your latest code, with all of your modifications.  20-30 seconds sounds way too long, as it you still have the writing to disk in there.

[Harjot]

Hi crossrulz

See in the attachment the RT Loging.vi and Bwave.iv (FPGA code). The RT looging.vi is a time critical vi (highest priority). However, we still have that loop running really at low rate of about 30s. So we still wonder what's make this loop to run so slow when only is handling reading fifo methods. Due to this delay of course our fifo gets full by the first time the loop runs on the RT.

many thanks! 

[Harjot]

The fpga shoot here.