DMA FIFO producing random data?

[Jimbo76]

Hi all,

Just to state upfront, I can't share VIs due to IP issues etc ... sigh.

Basically I have an sbRio 9626 and software running on the FPGA to interface with external analogue-to-digital converters. This is done using a state machine (single cycle timed loop with a case structure inside so it transitions between cases each tick of the FPGA clock). Inside one of the cases (states) I have a little routine which takes data from an ADC and places it in a target-to-host DMA FIFO buffer. In fact, there are 4 DMA FIFO buffers sending various information along with the sample value. This is then read by software on the RT Host and processed to produce an array of values which I then send to the PC using a shared network variable.

What I wanted to check was that the data being sent from FPGA to RT Host (and to PC) is contiguous (i.e. I have my FIFO lengths right). I modified the FPGA code to use a counter instead of the sampled data so the FIFOs should simply send numbers in a sequence (1, 2, 3, 4, etc). I then examine that sequence to ensure it's correct and no data has been overwritten.

What I find is that FIFOs 2, 3, and 4 are fine. FIFO 1 sends data that is continuous but every now and then I seem to get a random glitch. This glitch does *not*  appear to be due to FIFO lengths but seems to be an error in the data transfer. For example, I'll get something like 1, 2, 3, x, 5, 6, 7, y with x and y seemingly random values. The positions of x and y in the sequence are also seemingly random - they don't occur at the same point each time. The code writing to FIFO 1 is *exactly* the same as the others - in fact, it's the same dataset being written.

Anyone seen anything like this before? I'm trying to determine whether it's due to the target to host FIFOs or some problem with the network shared variable. I do a reset at the end of the RT Host software to clear everything before I re-run it. Any suggestions as to what I might check? It almost looks as though there's EMI spikes on the transfer ... not suggesting that's the case but it gives an idea of what I'm seeing. I'm using Labview 2013 and BIOS on the sbRio is up-to-date. 

[speleato]

Hey Jimbo76

Where are you checking the data? Is it on the RT Host after reading from the FIFO? Or on the PC after sending the data over the shared network variable? Neither should result in data glitches like you are seeing, but it'd be helpful to know how narrowed down it is. If you aren't doing so already, can you check the data on the RT Host, as close to the FIFO Read as possible?

A few other questions

- Have you re-compiled your FPGA VI at all? Does the failure persist across recompiles? If possible, it'd be ideal if you could hang on to a failing lvbitx file in case it doesn't reproduce

- Does the failure occur if the other FIFOs aren't sending data?

- Another thing you could try if your code allows is to change the FIFO that the Write and Read nodes refer to but leave everything else unchanged.

Are you able to post your code?

Thanks,

Sebastian

[Jimbo76]

Hey Speleato,

At the moment the data is checked on the PC after the shared network variable has transferred the data. I will have a look on the RT Host immediately after the FIFO Read as you've suggested. One thing I have just noticed which I'll check some more is that the glitches seem to become more frequent if I stress the PC (opening files while the acquisition is taking place, for example). Could be a fluke so I'll test that more thoroughly.

I'll try recompiling the FPGA VI as you suggest and hold onto the 'old' lvbitx file. And I'll check the failure if the other FIFOs aren't sending data. Afraid I can't post the code. Thanks for the suggestions though  ... I'll give them a try and report back once I've tried them!

Cheers,

James

[speleato]

Hi James,

Sounds good. Let me know what you find. One other thing you could consider doing is writing the simplest possible application that reproduces the issue. That would help eliminate possible sources of the error, and maybe it's something you would be able to share if required for further debugging.

Sebastian

[Hansel]

I'm sorry, this is an old post.  But did you find a solution to the problem you described??  I may be experiencing a similar issue.