DRAM from FPGA badly written at application start

[Pierre_F]

hi! I have a strange behaviour with my LabviewFPGA code joined in ZIp file (LV2019)

At program start, is to be automatically configured a DRAM signal with a 100k points at init

the problem: if I launch the main RT (RT test intersectif.vi in the zip file) once after compactrio power supply ON, the DRAM is not configured correctly, and I get noise (below) 

if I try again to run the VI, the signal becomes correct.

everytime I get 1st run time NOK and the 2nd one OK, whetever the time I wait between power ON and 1st start

I absolutely need this signal DRAM to be correctly uploaded at start.

Is there something wrong in my code?

thanks in advance for the help

[Terry_ALE]

DRAM handshaking is not connected fully