DRC warnings in LV FPGA-Modul

[beckerg]

Hi,
I am using LV 7.1.1 with FPGA-Modul 1.1.
Last week, I started to get DRC warnings in the compiler-log:
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Running DRC.
mytop_n_133762400_resVI_n_139936640_uut/B5 is not connected.
mytop_n_133762400_resVI_n_139936640_uut/B5 is not connected.
mytop_n_133763768_resVI_n_139792112_uut/B5 is not connected.
mytop_n_133763768_resVI_n_139792112_uut/B5 is not connected.
mytop_n_117965800_resVI_n_132097136_uut/B5 is not connected.
mytop_n_117965800_resVI_n_132097136_uut/B5 is not connected.
mytop_n_133765136_resVI_n_135911624_uut/B5 is not connected.
mytop_n_133765136_resVI_n_135911624_uut/B5 is not connected.
DRC detected 0 errors and 8 warnings.
----
Are they something I should worry about?
Any hints about how I can fix things to get rid of them?

[Christian_L]

Despite the warnings, is the VI able to compile correctly and run? Could you include the VI for reference so that we can provide more detailed suggestions?

[Christian_L]

These warnings are normal for the compile process. They indicate signals that are left unconnected within the FPGA, but that does not affect the operation or performance of your VI on the FPGA.

[beckerg]

Thx for the info.
I didn't had the time to check if I am allowed to post sourcecode, so you really helping me here.
Greetings
Goetz Becker