Data Transfer between FPGA and RT using FIFOs

[JoseFelgueiras]

Greetings,

I am trying to learn how to make my cRIO's RT receive data from the FPGA through a FIFO.

I know how share data between VI's via read/write controls, but I've been advised to use FIFO, since I'm developing an application for data acquisition and logging.

In my project (see image files), I've configured a FIFO and created an FPGA VI that writes some numbers generated for testing purposes only.

Currently I haven't managed to understand how to make the RT have access to the FIFO's data. When I try to deploy the RT code shown in the images, I get error messages.

[GerdW]

Hi Jose,

LabVIEW comes with ready-to-use example projects.

Why don't you open such an example project, explaining data transfer between FPGA and RT?

[cbutcher]

I suspect you need to actually start and run the FPGA VI within the RT VI.

Something using the following VIs: Open FPGA VI Reference and Invoke Method (e.g. Run). 

As Gerd said, there are existing examples that will show this (this is taken from the "Streaming Data (FIFO)" example found via searching for "dma fifo" in the Example Finder):

[JoseFelgueiras · Accepted solution]

So, I tried some different things and it turned out I had to change my FIFO from "Target-scoped" to "Target-to-Host DMA".

This gave access to additional options when adding "Invoke Method" block to the RT's VI.

I then made the RT VI read the dummy data stored in the FIFO and sequentially saving it into a flash drive.

I will look into optimizing this when I start developing for my application proper.

[cbutcher]

Yes, that looks much better (especially the RT picture)!

Sorry for not being clearer - I didn't see that the FIFO wasn't a DMA FIFO (although hopefully the search term I gave hinted in that direction).

The png files you attached don't display a difference for Target Scoped vs DMA (at least, that I could notice) and although your RT picture seemed strange, I thought maybe it was a different (valid) way to access a FIFO. In particular, I didn't imagine a Target Scoped FIFO would be possible to drag onto a RT block diagram...

[MrJackHamilton]

The FIFO and DMA examples lack any introduction as to their intent, and often have additionally complexities that don't clearly outline the basic methods to write data to the FIFO reliably and then upon reading the FIFO on receipt polling the FIFO in a robust way to capture the data efficiently.

Streaming data from the FPGA to the Host should have a very straight-forward example...however there is not one.

Also, reading the FIFO on the RT side consumes substantial RT processor overheard, because to appears to only provide for polling the FIFO buffer on the read, by running a wide-open RT loop with no interrupt. The FIFO model would be better implemented with an integrated interrupt. 

The Handshake FIFO method is not support across all cRIO, myRIO platforms - so the time spent code it - is wasted.

Nearly every time I have to code a FIFO from FPGA to RT, or the Host I have to re-learn how to basically code it...then spent time 'optimizing' it on the RT to catch all the data in buffer. [Or pull up some old code]

I'd be happy to be shown a elegant simple example of a FIFO sending data from the FPGA to the Host.