Helo,
I have created a LabVIEW project for cRIO 9047. It is about controlling motors via motor drivers and creating a simple control via received sensor data. The interface of the sensor data runs via OPC UA and has a maximum clock rate of 200ms. The control and regulation of the motors does not have to be fast for the application (20ms is sufficient as a clock):
- Motor drivers are controlled via the FPGA. The StateMAchine is located there
- The user interface on the cRIO accepts the operator's input and sends it to the StateMachine on the FPGA.
- The sensor data is not yet taken into account in this programm.
I divided the code into MainVIs: cRIO-Main, FPGA-Main.
The following problem occurs, which I cannot solve:
- with the cRIO-MainVI I get error 1 (in all SubVIs with the Notifier). I have already read that the problem may have to do with the timing, as the GetNotifier does not receive a value. If i run the programme with the UI without cRIO and only on the PC, the exchange of data via the notifier was no problem. It is clear at any moment which state is present and which values the various controls and indicators have in the clusters. Where does the error come from and how can I fix it?
Is the problem in the FPGAVI?I have two while loops here, one where data comes from the cRIO and another where data goes to the cRIO. I have divided the code into MainVIs: cRIO-Main, FPGA-Main.
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The following problem occurs, which I cannot solve:
- with the cRIOMainVI I get error 1, in all SubVIs with the Notifier (see in picture)
I read in the forum that the problem may have to do with the timing, as the GetNotifier does not receive a value. If i run the programme with the UI without cRIO and FPGA and only on the PC, the exchange of data via the notifier was no problem. It is clear at any moment which state is present and which values the various controls and indicators have in the clusters. Where does the error come from and how can I fix it?
Is the problem in the FPGA VI? I have two while loops here, one where data comes from the cRIO and another where data goes to the cRIO. From this loop the data is sent to the second loop with the state machine. From the state machine, data comes back to the first loop, which go back to the cRIO.
Is it because the loops are not clocked the same?
Shall I put everything in one loop in the FPGA VI?
Shall i use an other option (ex FIFO, memory blocks) to transfer data?
That's a lot of questions at once. However, the first point is the most important one, so that the programme runs at all in the first place.
I would be happy about your feedback and thank you in advance for your answer!
Regards
Azoth
