Debugging Labview FPGA code that contains HDL Interface Node

[pradfernando]

Hi

    I am kinda new to Labview and Labview FPGA. I am trying to create testbenches in Labview for a HDL project. I am using the HDL Interface node in Labview FPGA and instantiating my design in it. I have tested simple AND and 8-bit REGISTER designs using this set-up. But when I use my design (which is a pretty simple controller in VHDL) the code compiles and runs but does not respond to any of my inputs. I suspect a problem with my enable chain but am not able to find what it is as all the debugging utilities are not available (disabled). Can anyone tell me how to go about debugging my design?

Thanks,

Prad.

[Nick R]

Hi Prad,

Debugging designs using the HDL node can be tricky because you cannot use any of LabVIEW's built in debugging tools. The best way to debug is to generate your enable chain testbench and take this back to your VHDL envinroment to test it out. Atlernately, you could add additional outputs to your HDL node in order to probe information to get a better idea of where the problem lies. I hope this helps!

[Nick R]

Just to clarify, you can generate your enable chain testbench by double clicking on the HDL node, selecting the simulation tab, and then click on "Generate Enable Chain Testbench". There is also a lot of detailed information in the LabVIEW Help on the HDL node. If you open the LabVIEW Help and search for HDL you will find this information.