Design does not meet the timing constraints of the specified clock

[SunJab]

Hi,

I am using labVIEW FPGA 2011 and FlexRIO 7965R (virtex 5 SX95T). I am trying to use multiple simple dual port RAMs (generated through xilinx coregen tool) in cascade. The data read from one memory block is written to the next memory block and so on. I want the design to run as fast as possible. I have used SCTL rate of 346MHz in my design. But when i compile the code, timing violation error occurs. And the maximum clock rate achieved is 291.25MHz. The timing vilation analysis window always show the feedback node and controller as paths which failed to meet the timing contraints. I have also used DMA and VI Scoped FIFOs in my design for data input and output. 

I have attached the code and images for xilinx block memory generator IP configuration settings. Kindly have a look at my code and tell me what is it that i am doing wrong? what are the considerations for pipelining the design? cause i have tried placing registers after every stage in my code but this reduces the clock rate to even below 291.25MHz.

Thanks

[SchamWow]

Have you taken a look around the forums?

http://forums.ni.com/t5/LabVIEW/Compile-Error-in-FlexRIO-FPGA-when-using-derived-clock/td-p/1617226

What is the exact timing violation error you receive?  Depending on how your feedback nodes are used it can slow down the clock rate from the desired clock rate.  This is what I normally use as a reference for making my code operate more quickly:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/registers/#Register_Timing

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/fpga_timed_loop/

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_pipelining/