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Digital Output on an FPGA

I am currently using the PCIe-7842R FPGA, and I am trying to control an acoustooptic deflector via a direct digital synthesizer from AAOptoelectronics. The flow of my setup goes FPGA->connector block->DDS->AOD. I have wired up my DDS to the connector block using the pinout diagram provided, and have written the simple code attached to this post to control the DDS...it runs and compiles, but does not actually control the DDS. I have attached an excerpt from the DDS manual as well, and any advice on why my code isnt working would be much appreciated!

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What behavior are you experiencing when you say it does not control the DDS? Have you tried controlling the DDS without using the FPGA to make sure that the device itself works and is controllable?

Conner A.
Technical Support Engineer
National Instruments
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@JCard wrote:

I am currently using the PCIe-7842R FPGA, and I am trying to control an acoustooptic deflector via a direct digital synthesizer from AAOptoelectronics. The flow of my setup goes FPGA->connector block->DDS->AOD. I have wired up my DDS to the connector block using the pinout diagram provided, and have written the simple code attached to this post to control the DDS...it runs and compiles, but does not actually control the DDS. I have attached an excerpt from the DDS manual as well, and any advice on why my code isnt working would be much appreciated!


I'd start by controlling the DDS with some manual digital signals. Bypassing the FPGA completely. Those DDSs might have an enable and\or mode select and\or a select\clock in bit... Not sure what else it needs, maybe an input frequency.

 

If you can't get it working this way, it won't work with the same bit pattern from the FPGA.

 

Once you have a working bit pattern, replicate that pattern from the FPGA, statically.

 

If it does work with a manual bit pattern, it's only a matter of figuring out why the FPGA pattern doesn't work. I'd be suspicious about the first bit being 1, instead of 0, and perhaps the bit order (MSB first\LSB first)

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Hi Connor, yes, the DDS works without the FPGA. I will send the signal in order to get the beams to deflect and the code complies and runs just fine, but no beam scanning is happening

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So, what's different? Do you have a logic analyzer or memory scope? That usually clears things up. You'll need to find out if what you're doing is what you expect. I doubt we can assist much... Perhaps with code and manuals.

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