Do shift registers have less propagation delay than feedback/forward nodes?

[Idratherberacing]

I am trying to do a bunch of stuff in an SCTL and it's either the feedback nodes or the calling of several subVI clones that is slowing it down too much.  Any input here is appreciated.  Thanks!

[Ben]

The "experts" say no and favor the feddback over the SRs. I can't confirm this since I have avoided them due to bugs in early releases and a lack of motivation to benchmark them.

If you want more help, please post image of your your actual code and tell us where to start looking.

Ben

[JICHFI]

I think Feeback nodes are faster

[smercurio_fc]

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Idratherberacing wrote:
it's either the feedback nodes or the calling of several subVI clones that is slowing it down too much. 

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This is a bit too vauge. What's in your feedback nodes? What kind of operations are you doing? Are you building an array, increasing the memory footprint? What do your clones do? How many clones are you opening?

[rolfk]

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Idratherberacing wrote:
I am trying to do a bunch of stuff in an SCTL and it's either the feedback nodes or the calling of several subVI clones that is slowing it down too much.  Any input here is appreciated.  Thanks!

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The first implementation of the feedback nodes in LabVIEW 8.0 were a lot slower than a shift register because the person implementing them was creating completely new (and rather bad) code for them. In 8.2 or 8.5 the feedback node got redisigned to use internally exactly the same (highly optimized) algorithme that is also used for shift registers. As such I would not expect any measurable difference between the two but have never benchmarked them since I find the shift registers to be more intuitive to use.

Rolf Kalbermatter

Message Edited by rolfk on 08-12-2009 05:03 PM

[Idratherberacing]

I am basically using the registers or the nodes as counters.  I am passing U16 data to the next cycle from the current cycle and checking the data from the previous cycle in the current cycle. 

I have two implementations for this.  One uses one feedback node and one feedforward node.  The other uses two shift registers.

This one subVI gets called/cloned 19x2x3 = 114 times in a single cycle timed loop @ 40MHz FPGA clock rate.

[Ben]

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rolfk wrote:

... have never benchmarked them since I find the shift registers to be more intuitive to use.

Rolf Kalbermatter

Message Edited by rolfk on 08-12-2009 05:03 PM

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Same here!

Ben

[Matthew_Kelton]

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Ben wrote:

The "experts" say no and favor the feddback over the SRs. I can't confirm this since I have avoided them due to bugs in early releases and a lack of motivation to benchmark them.

If you want more help, please post image of your your actual code and tell us where to start looking.

Ben

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The experts might say no, but in benchmarking it in this thread, the feedback nodes are still significantly slower.  I did some testing in 8.6.1f1 since my original post only went up to 8.6 and am seeing the ratio has gone up again to 1.55 with peaks in the 1.6 range.  I haven't had the chance to install LV2009 yet, so can't comment on its speed.

[Ruhmann]

It sounds like you're using the single cycle timed loop in LabVIEW FPGA.  This is a very different thing than the timed loop in RT (which is what I think most of the people on this thread are talking about).  To my knowledge, there is absolutely no difference between a shift register and a feedback node in the LV FPGA SCTL.  They should both be imlemented as a simple set of flip flops in the FPGA. 

Are you getting timing failures from the Xilinx compile or is LabVIEW telling you that you can't use the nodes in a SCTL?

[Idratherberacing]

I'm getting timing failures in the compile server.  It could just be the amount of data and processes being done, but i had no issues until i started using feedback nodes, which led me to ask this question...