10-24-2025 12:49 PM
I am using a NI-9145, with NI 9361 cards. I am using logic threshold 1V, single ended and digital filter of 1250 unit ticks (0.1ms). the cards are set up to detect rising edge. and give me the number of detections evertime i read with my timed loop
(synced with scan engine.) but occasionally even with a signal generator from an oscilloscope. im getting double pulses occasionally, its intermittent. this has led me to believe its the software on not any noise within the system. Is my timing set up incorrectly?
10-27-2025 08:20 AM
The problem is that I am reading from the scan engine before it updates. That why my counter card is reading duplicate values.
How can i properly time this loop with the scan engine? I am following from the NI example "User-Defined Variable IO Scan Sync".
When moving the Feedback nodes from the FPGA side to the Realtime side, the repeated values, causing duplicates, no longer persists. But that also means I am reading from the scan engine before it has updated its values.
What can I do?
10-27-2025 08:36 AM
10-27-2025 12:34 PM
GerdW,
I have left it at the default of 1ms. Is this a bad design? Its a NI-9145 and cRIO-9049, top of the line. so it should be able to handle 1000hz.
I am considering moving the I/O Nodes from the Scan Clock "Wait on Rising Edge" Frame. IF that would eliminate the double reads from the cRIO end.
Unless you think I can just remove the "Wait on Rising Edge" entirely?