10-09-2017 01:31 AM
I am new to Lab View to FPGA programming, I want to design a filter using Xilinx IP Core in Lab View FPGA, when I put the xilinx IP core for Filter from FPGA Pallet in Lab View and Lunch the core and after putting all parameters in xilinx core during the generation it gives the subject error. I am using Lab view 2012(32 bit) and Flexrio 7965R. Please help me in this regard Thanks
10-09-2017
03:05 AM
- last edited on
01-10-2025
06:07 PM
by
Content Cleaner
Not sure if it helps (there's no solution or workaround) but it is known issue 364903 in LV2013:
Only hint it gives is it happens on "slow" PC's. So upgrading might help (might upgrade LV as well). Hardly a solution, I admit.
I'd also turn off anti virus checking for the FPGA folders that LV use. This can significantly slow down and\or break compilation. Had problems with Kasperski in the past. Not sure if it was this error though.