Example of High pass filter for FPGA

[Shivkumar]

Dear Labview users,
                                     I am using compact rio 9002 & FPGA 9101 and labview 8.0.  A signal of 1kHz of sine wave with some DC components will come from a photo detector, here what i have to do is getting only the 1kHz sine wave signal rejecting the dc components. We have newly bought digital filter design tool kit also, but i dont know how to program a high pass filter cut off frequency of 800Hz in the FPGA side with this tool. Can anybody help us by  ship an example of high pass filter cut off frequency of 800Hz for the FPGA side.

          Could anyone provides me a example would be great, because of my time constraint.

Labview Lovers.

[paulmw]

I am not fimilar with labView FPGA devices but if you only need to remove a DC component, would it be easy enough to add a series (DC blocking) capacitor in your connection?

[Christian_L]

In the Digital Filter Design (DFD) toolkit, look at Case Study 1 in the examples. This set of example VIs shows you how to proceed through the filter design process to creating your own filter for the FPGA.

..\LabVIEW 8.0\examples\Digital Filter Design\CaseStudy1

In step 1 you design the filter. By default this example is configured for a low pass filter but you can easily change it to a high pass filter. All the filter settings are made in the dialog of the Equi-Ripple FIR Express VI. Double-click on the VI and configure your filter there. As part of the filter design you need to know what acquisition rate you will use to sample the signal. See the attched screenshot.

Steps 2 through 4 allow you to analyze and test your design. You can skip these if you want.

In step 5 you will convert the filter design into a FPGA filter VI. Once you open this VI you need to make the same changes to the Equi-Ripple FIR Express VI as you made in step 1. Then select a file name for your FPGA filter on the front panel of the VI and run the VI. It will generate the FPGA filter VI and save it on your harddrive and open it as well. You can then insert this VI into your FPGA code.