FIFO Problem

[Wei Jin Tan]

Hi Guys,

I am currently trying to acquire voltage and current measurement data from an Analog Input Module 9201. The intention is to sample at 20kHz. I am using a Compact RIO 9022 with a 9113 chassis. I know I need to create a FIFO as a buffer between the FPGA and real time controller. The FIFO created in the project is a Target to Host -DMA (im assuming this is correct) with 12000 elements and a data type of FXP, signed 16 bits. In my FPGA VI, I set the loop to execute every 50us each time gathering 1000 samples from each of the 6 channels.

For testing purposes, I am currently using a signal generator to generate a pure sine wave of 50Hz with an amplitude of 5.

On my Real Time VI, im not sure if I configured the FIFO correctly. I used an Invoke Method to configure a FIFO with a depth of 40000. The VI loops at 100ms, each time acquiring 6000 samples ( 6*1000) of data. When I view the graph FIFO tester, the results were erratic, with moments of it showing a badly sampled stepped sine wave.

Also, I am intending to phase shift the signal using the Fourier based phase shifter shown in my VI. Instead of only phase shifting it, the signal is offset as well. I am not sure what is the problem with this part. I tried using a Hilbert Transform phase shifter ending up with the same problem as well.

Would really appreciate if I could get some help regarding this matter.

Thanks

[Wei Jin Tan]

Hi Guys,

I am currently trying to acquire voltage and current measurement data from an Analog Input Module 9201. The intention is to sample at 20kHz. I am using a Compact RIO 9022 with a 9113 chassis. I know I need to create a FIFO as a buffer between the FPGA and real time controller. The FIFO created in the project is a Target to Host -DMA (im assuming this is correct) with 12000 elements and a data type of FXP, signed 16 bits. In my FPGA VI, I set the loop to execute every 50us each time gathering 1000 samples from each of the 6 channels.

For testing purposes, I am currently using a signal generator to generate a pure sine wave of 50Hz with an amplitude of 5.

On my Real Time VI, im not sure if I configured the FIFO correctly. I used an Invoke Method to configure a FIFO with a depth of 40000. The VI loops at 100ms, each time acquiring 6000 samples ( 6*1000) of data. When I view the graph FIFO tester, the results were erratic, with moments of it showing a badly sampled stepped sine wave.

Also, I am intending to phase shift the signal using the Fourier based phase shifter shown in my VI. Instead of only phase shifting it, the signal is offset as well. I am not sure what is the problem with this part. I tried using a Hilbert Transform phase shifter ending up with the same problem as well.

Would really appreciate if I could get some help regarding this matter.

Thanks

[Rhys - AE]

Hi there Wie Jin Tan,

I must be honest, I'm no guru when it comes to RIO but I hope I can help out.

I'm looking into getting the same hardware as you and testing out your code to see if I get the same problems. Was the amplitude of your generated sine wave 5 Volts amplitude, 5 Volts peak to peak, or 5 Volts RMS? And was the scope set to expect a high impedance load (High Z) or did you have it on a matched setting which as default tends to be 50 Ohms.

Sampling a 50hz wave at 20Khz gives us 400 samples per cycle so I would also expect you to recieve a very smooth/true representation of your signal. A quick flick through the specifications sheet for the 9201 leads me to believe the module is perfectly capable of these speeds.

Let me know if you are still coming up against the same problems. I shall be back in touch to let you know how my experimentation goes.

Thanks!

[Wei Jin Tan]

Hi Rhys,

Thanks for the reply. Im generating 5V peak to peak from the Function Generator. I am not sure what load impedance setting is set on the scope, it does not have the setting available on the front panel. Today I tried a different example I found from the NI website. Its from http://zone.ni.com/devzone/cda/tut/p/id/11198.

I managed to get a perfect sine wave once, with a FIFO size of 16383 elements, Host VI running at 5ms intervals, and FPGA VI running at 50us. After stopping the VI and running it again, I was unable to obtain the similar results. It happened twice, I was getting the expected signal, and then when I stop the VI and run it again, it does not work.

Thanks for Your Help

[Rhys - AE]

Ok, maybe we are dealing with a problem due to the size of the elements, but before we investigate that:

I have seen this exact sort of behaviour when not closing the reference to an FPGA target correctly. The following part of the example VIs is very important, as it closes down the reference to and release the resources related to the FPGA target.

To close down a reference that has been left open, instead of restarting your PC and cRIO, you can usually run a VI which contains just this piece of code directed toward your FPGA target.

Because it's so important to close down the FPGA reference then we must always stop running out code using stop buttons and data flow, coming naturally to the end of our code. The red button in LabVIEW, the "abort button" , should only ever be used to escape the very worst hangs or crashes as a last resort.

Let me know if this helps. Thanks 🙂