FIFO not returning results in desired order

[BonbonBLou]

Hi guys,

I'm having a strange problem and wondering if anyone can give me a heads up as to what's going on.

I have a FIFO that I am trying to read as quickly as possible and bring all of the results back. I am adding 5 elements on the FPGA and reading them on the Real Time. However, when I read the results back, I am not getting element 1 back first - my results will start from  - for example, channel 3.

The results seem to always come in in the same order, just the data array doesn't start from channel 1 whenever I read.

I have tried writing the elements in a few different ways in order to get it working, but I'm still not having any joy.

Ways I have tried writing:

1) Using error wires to try and force the order of writing elements (as in screenshot)

2) Putting all of my channel readings into an array, and wiring that to a for loop, so it should index them and read each one in order

3) Writing the first channel to the FIFO and wiring the 'Timed Out' parameter to a case structure, so that it only writes the rest of the channels if it hasn't timed out.

In order to read the elements, I am first making sure I only read a 'number of elements' that is a multiple of 5, so that I am (in theory!) not reading half way through a set of elements. As I said before, the elements are always coming back in the same order, it's just they are not starting from channel 1.

I have determined this by hardwiring a 1 value as the 5th value for each set that I write, and seeing at what index it is read at. It tends to appear in my 'Slot 6 read' array around index 2 or 3 each time. 

I suspect there is a problem with the way I am reading somehow, but I am not very experience in using FIFOs so I am not sure. Any help will be appreciated. I have attached a screenshot of my FPGA and my Real Time code, so you can see how I have tried to do it.

Thanks in advance 🙂

[dan_u]

How big is your FIFO both on the FPGA and on the RT? Did you check the "Timed Out?" flags on the FPGA to see if it is ever full? Probably it fills up at the beginning on the FPGA side so it can't write some elements.

[BonbonBLou]

Ah yes! The Write methods were timing out when the RT wasn't running.

However, would you expect if it was missing elements, that I would be geting my channel results in a completely random order? Or am I missing the point?

Any way, is there an easy way to prevent it filling up? i.e - only writing elements if the RT is running?

[Intaris]

It's not a random order, like you said yourself, the order is correct.

If the FIFO is full, no new values will be added until you have read something after which continuously new data will be provided.  The problem is that your FIFO size on the FPGA is not a multiple of your packet being sent (32 maybe?) so when it is full you're losing PART of a packet, hence your data does not start at 1.

Shane.

[crossrulz]

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@vascibean wrote:

Any way, is there an easy way to prevent it filling up? i.e - only writing elements if the RT is running?

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Use a boolean command to enable/disable the logging into the FIFO.  It should be FALSE by default.  Then when the RT system is ready, the RT can set the boolean to TRUE and start getting the data.  It might be a good idea to increase your FIFO size as well.

[dan_u]

Well you could for instance check the "Number of Elements to Write" at the beginning of each FPGA cycle. If it is less than 5 skip all write to FIFO nodes for this iteration.

Of course you have to decide how to deal with this "data loss". Maybe it's ok for this application, maybe not.

[BonbonBLou]

Hi guys,

Thank you all for your input. I have tried all of your suggestions, however it doesn't seem to have solved my problem.

I am no longer seeing any timeouts, but my results array is still not coming out with the first channel at index 0 etc.

To make it clear, the changes I have made are:

- Increased the number of elements requested in the FIFO, and made sure that it is a multiple of the number of channels I am reading.

- Added a boolean control and a case structure to the FPGA to write elements only when it is set to true on the RT (which it does after the Start).

- Inside this case structure, have put another so that elements are only written when the 'number of elements to write' is greater than my number of channels.

Do you have any other suggestions as to what might be causing this problem and how to fix it?

Thanks in advance,

Lou

[dan_u]

When talking about "elements requested" it looks like you set the FIFO size on the FPGA.

Did you also set the size on the RT? Should be bigger (probably 4x) than the size on the FPGA.

You might want to use the FIFO.Configure method on the RT (and probably also the Stop method before the Start method) to set the size of the FIFO on the RT and flush it. If you don't flush it you might have unread elements left in the FIFO causing your shift.

[BonbonBLou]

Hey,

 I have now tried stopping the FIFO before starting it, and have increased the 'Requested Depth' like you said, but again it doesn't seem to have made any difference.

This is currently what I have after making all of the changes that have been suggested to me.

FPGA Code:

Real Time Code:

Can anybody see where I'm going wrong, or have any other suggestions that I have not tried yet?

Any ideas are welcome, I'm getting slightly frustrated with this now! 😛

Lou

Edit: Actually added the VIs as an attachment aswell as the screenshots look a bit small!