FIFO - slow write/ fast read, Problem?

[juanpablo.pascual]

Does this technique help for independent clocks, for example a timed loop with a 65MHz (derived from the 40MHz internal clock) for writing data  and another timed loop with the 130MHz clock of the FlexRIO module for reading data?  Do I have to take care about no sincronization at all between edges of the clock? Thanks!

[Terry_ALE]

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@juanpablo.pascual wrote:

Does this technique help for independent clocks, for example a timed loop with a 65MHz (derived from the 40MHz internal clock) for writing data  and another timed loop with the 130MHz clock of the FlexRIO module for reading data?  Do I have to take care about no sincronization at all between edges of the clock? Thanks!

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Target Scoped FIFOs are for crossing clock domains, so yes.