FIFOs and Assembling Data

[nslogan]

That...makes a lot of sense. The only part I'm not 100% on is what you mean by:

---

nathand wrote:

  you move all the control logic to the FPGA

---

As far as designing it to fit my application, there are times when the engine won't be running and thus there won't be a change in Crank Count so I have to be able to handle that. I could probably tie the DMA read to SyncEnable or something similar and then figure out my CAD sync to 0 like we talked about before.

[nathand]

What I meant was, whatever function it is that you're calling now from the RT code, you could handle instead on the FPGA. But I just looked again and I see that it's the watchdog and it's probably best to leave that on the RT side.

Another fairly easy solution is to read 0 elements out of the FIFO with a 0 timeout on each loop iteration. Check the Elements Remaining output; if it's greater than or equal to the number of data points that you want to read, then do another read for that many data points and do the processing. This won't require major changes to your existing code, and will handle the case where there's no data in the DMA data buffer at all.

[nslogan]

IT WORKS!

I can't begin to thank you enough, I've been working on this for weeks to no avail.

It's still a little choppy right now but I haven't done any math to figure out how large my FIFO needs to be, how frequency I need to service the loop, etc. and I'm sure once I do it'll smooth out the results. Now I can actually begin to add the stuff you were talking about - reading until you find 0 and then reading 720 elements at once, etc.

I've attached the code I put together quickly to test it out (so it's probably really bad) so you could see what I ended up doing.

[nslogan]

Let me know if you think this sounds like a good idea.

I really only want data whenever the engine is on and SyncEnable = TRUE so I could use that as a trigger to sync the FIFO to the engine - thus, whenever the next 0 CAD comes up I use a Clear FIFO and start writing to the FIFO again. Then on the RT time I should get data that is synced to 0 CAD and coming in a very managable rate (1000 RPM @ 360 tics per rev, 1 cycle = 720 tics -> 120 ms per full cycle).

[nslogan]

And then I have one additional DMA FIFO question. I'm using the second method you talked about, reading 0 and then reading the number left (seen in the link you provided); however, if I read a fixed amount - say 720 - instead of the number left the data seems to go extremely slowly and the Crank Count decreases rather than increases. Any idea why? I've attached my RT code where I can switch between reading max and reading fixed.

[nslogan]

It seems there's not a Clear method for my FIFO so that's out I guess.

[nathand]

There isn't a good Clear FIFO method. There's an error in the documentation about stopping a DMA FIFO. That said, it isn't too hard to read out elements until it times out to make sure the FIFO is empty. Your synchronization scheme sounds reasonable from there, given my limited understanding of your system.

I'm not sure what you mean by "data goes extremely slowly." How large is the difference between 720, and the number of elements that are available. If there are 7000 elements available and you only read 720 of them, then of course it will look like the data is updating slowly, because you'll only be adding 1/10th as many elements to the graph on each cycle. That also suggests that the DMA FIFO is filling, so you're probably losing some data, which could explain why the data is showing a decreasing crank angle.

[nslogan]

The difference between Left and 720 is generally 50 to 100 elements (except for the first read after it's been stopped which is much larger, maybe 800 or 1000).