I'm trying to use VHDL code as CLIP component (following this tutorial here). After compiling on FPGA I get bunch of warnings and errors and after executing it on computer the output goes nuts (rapidly changes).
Do you think you could include a screen shot of the window that shows the errors after you are done compiling? Also, take a look at this document, make sure that these were the steps you followed in setting up your VHDL as a CLIP component. I hope this helps!
