FPGA CS Line

[arosss]

Hi all, 

First of all I've attached code and the instrument I am trying to communicate with. The main goal of this project is to read the FIFOs from the board. I've set digital outputs of a myRIO-1900 to SCLK, MISO, MOSI, and CS0.

It's my understanding that the chip select line should only drive high after a command has been written to the device. I have wired up waveform charts to show DIO activity in the FPGA code which I have screenshot of as well attached. I would think that the CS should drive up periodically but it seems that it is "sporadic" if you will. It does not look uniform. 

It should drive up after 2 U8 bytes are clocked in by the SCK. Am I doing something wrong in the FPGA? Is this normal operation? 

Thank you. 

[Bob_Schor]

It is completely unclear (to me) what you are doing, and what you are trying to do.  I presume you already know that the myRIO is a perfectly-capable "SPI Master" -- the myRIO Software Toolkit even comes with Express VIs that implement two independent SPI Master devices using the DIO Lines on MXP A and B connectors.  Do a Web Search for myRIO SPI for a useful Video of how to do this.

Bob Schor

[arosss]

Just trying to communicate with my device I'll give a look over what you recommended. 


Thanks Bobby.