FPGA Checksum

[cbmeixell]

Hello All,

I am looking to get some form of a checksum back on what is loaded on an FPGA card.  I then would like to compare this checksum to the compiled bitfile.  If different, load the bitfile.  Otherwise, start running.  This is an attempt to limit the number of loads on the FPGA and therefore make the card last longer.

Is this possible?

Right now, I have a hard coded indicator in the FPGA code that I have to update each time I create a new build.  The host application checks the value of this indicator and determines if it should download the bitfile based on the result.  This is something that can be forgotten down the road, so I would like a better solution.

Thanks!

[nathand]

My understanding (from internet searches) is that FPGAs do not wear when you download a bitfile, so there's no need to worry about this.

[cbmeixell]

The FPGA itself may have an "unlimited" number of writes.  However, it is my understanding that you are really flashing an EPROM with your bitfile which upon startup loads the FPGA with its configuration.  Depending on the type of memory you are writing, there are a limited number of writes.  Although the number is on the order of tens of thousands, it is our intention to prevent limitations on the life of the teststand this card is going in.

Besides, wouldn't adding such a function be good practice anyway?  Could the "download" FPGA node already be doing this behind the scenes?

[DylanC]

Hi cbmeixell,

The limit of flashing the EEPROM should be well over a million. How often are you planning on flashing the EEPROM?

Opening the reference from RT downloads the bitfile, but does not download it to the Flash memory, so this does not apply to the number of the times the FPGA memory can be flashed. This is dependent on the number of times the FPGA fabric can be changed, which is much more.

Here is a great link on managing FPGA deployments:

http://www.ni.com/white-paper/9640/en

DylanC

[nathand]

Dylan - could you comment on this somewhat vague Knowledgebase article on this topic: Is There a Limit to How Many Times You Can Write to the FPGA on the 783x board?

[DylanC]

Hi nathand,

Any specific part of that you need clarification on? You can also use this KB:

 http://digital.ni.com/public.nsf/allkb/ed6fc9cf7b983cfd86256dce0072e313?OpenDocument

To find information from on the specific FPGA chip for each board.

"NOR technology can support up to one million program/erase cycles without requiring error correction, whereas NAND technology requires error correction much sooner (closer to the 100,000 range mentioned earlier)."

DylanC

[nathand]

I don't see anywhere that specifies which type of flash is in a given FPGA board.  Also, the manual for the 7813R (for example) says:

"The FPGA does not retain the VI when the R Series device is powered off,
so you must reload the VI each time you power on the device. You can load
the VI from onboard flash memory or from software over the bus interface."

So, does that mean that the FPGA bitfile is loaded directly out of RAM, or is first loaded into the FPGA board's flash?

[solarsd]

Hi,

I would like to reopen this discussion. FPGA lifecycle aside, is there a way to calculate the checksum of the bitfile currently on the FPGA? Sometimes when I make changes to a FPGA program, recompile it and download it to the card the changes are not there and I have to download the bitfile again. It would be great if I just could compute the checksum - a standard practice really.

Thanks.

[WishKebab]

Hi solarsd, 

Unfortunately, I can't think of a good way to read the bitfile that is currently on the FPGA (and use that information to compute a checksum).  It would certainly be useful, but I haven't run across how to do it.  Perhaps someone else can help us out?

[T-REX$]

If you open up any .lvbitx file in notepad(++), you'll notice some XML wrapping a bunch of gibberish. One of the XML tags is <SignatureGuids>. This should be a hash unique to your each build. Alternatively, you could start writing and reading the version info each build, and use that XML tag (more useful IMHO). There isn't a public API for parsing bitfiles, but I'm sure you can write some functions to ftp the bitfile off the controller, and compare the 2 tags. This won't get the bitfile off the FPGA (that's not possible), but will at least compare to your start up app that is stored on the RT controller. 

My recommendation is to add version registers to your FPGA front panel, and read those. You can even do it at run-time... which seems to be closer to the behavior that you want, it just requires some level of build management on your part.