FPGA Compile Broken

[Gryffin]

That is certainly a workaround for a few additional targets, however, it is quite inconvenient.

I want to add further permutations of cRIOs and C series card combinations, which will ultimately entail multiple more projects.

Also, my "mass FPGA compile .VI" can only operate on a single project at a time, thus, I would need to individually go into each project and run the VI for each...

Not to mention that "logically" speaking, all of these targets are part of a single "project", and if it werent for the 2 GB ram limitation, I could continue to add them.

Ultimately, I hope NI adds support for 64-bit cRIO FPGA programming soon, as this is the only real solution.

[Terry_ALE]

I used to confine a work project to a single LabVIEW project file.  I no longer consider this a valid development guideline.

In other IDEs they have workspace files which contain groups of projects.  A single project also limits scaling the team and modularizing things for other projects.

I do not know about the other constraints but I wonder if there is an easier way.

[XM43]

Hi Gryffin,

My case may not be applicable in your case but should not hurt to try. I have recently been getting this error while trying to compile an FPGA VI while a VI is currently running on the FPGA. I do not recall this being an issue previously.

In my case, I have sbRIO connected in the project (green indicator), I have my RT main VI running which loads a startup FPGA bitfile if the RT main VI is running. So basically I would shut it down, meaning no VI is running on the FPGA and now I can compile the code.

I am running LabVIEW 2019 32 bit.

I have another issue where if the compilation fails once and I re-try to compile I cannot do so until under the tray icon I right click on FPGA compile farm and choose close immediately option.

[Gryffin]

Thanks for the suggestion XM43, however, that is not the case for me.

All my targets were offline during these attempts to compile, thus, there was no connection to any of them and none were running the FPGA VIs.